74AC520 Fairchild Semiconductor, 74AC520 Datasheet

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74AC520

Manufacturer Part Number
74AC520
Description
8-Bit Identity Comparator
Manufacturer
Fairchild Semiconductor
Datasheet
©1989 Fairchild Semiconductor Corporation
74AC520, 74ACT520 Rev. 1.4
74AC520, 74ACT520
8-Bit Identity Comparator
Features
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
FACT™ is a trademark of Fairchild Semiconductor Corporation
74AC520SC
74ACT520SC
74ACT520SJ
74ACT520PC
Compares two 8-bit words in 6.5ns typ.
Expandable to any word length
20-pin package
Outputs source/sink 24mA
ACT520 has TTL-compatible inputs
Number
Order
Package
Number
M20D
M20B
M20B
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
.
General Description
The AC/ACT520 are expandable 8-bit comparators.
They compare two words of up to eight bits each and
provide a LOW output when the two words match bit for
bit. The expansion input I
LOW enable input.
Pin Descriptions
Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
Note:
1. A
A
B
T
O
Pin Names
A = B
0
0
Package Description
A = B
–A
–B
0
= B
7
7
I
A = B
H
L
L
H
0
, A
1
= B
Inputs
Word A Inputs
Word B Inputs
Expansion or Enable Input
Identity Output
1
, A
2
= B
A = B
A = B
A ≠ B
A ≠ B
A, B
A = B
2
, etc.
(1)
(1)
Description
also serves as an active
Outputs
www.fairchildsemi.com
O
March 2007
A = B
H
H
H
L
tm

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74AC520 Summary of contents

Page 1

... Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Connection Diagram FACT™ trademark of Fairchild Semiconductor Corporation ©1989 Fairchild Semiconductor Corporation 74AC520, 74ACT520 Rev. 1.4 General Description The AC/ACT520 are expandable 8-bit comparators. They compare two words eight bits each and provide a LOW output when the two words match bit for bit ...

Page 2

... Logic Symbols Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1989 Fairchild Semiconductor Corporation 74AC520, 74ACT520 Rev. 1.4 IEEE/IEC 2 www.fairchildsemi.com ...

Page 3

... Applications ©1989 Fairchild Semiconductor Corporation 74AC520, 74ACT520 Rev. 1.4 Ripple Expansion Parallel Expansion 3 www.fairchildsemi.com ...

Page 4

... O T Operating Temperature A ∆ ∆ t Minimum Input Edge Rate, AC Devices: V from 30 ∆ ∆ t Minimum Input Edge Rate, ACT Devices: V from 0.8V to 2.0V ©1989 Fairchild Semiconductor Corporation 74AC520, 74ACT520 Rev. 1.4 Parameter Parameter , V @ 3.3V, 4.5V, 5. 4.5V, 5. Rating –0.5V to +7.0V –20mA +20mA –0. 0.5V CC – ...

Page 5

... All outputs loaded; thresholds on input associated with output under test. 3. Maximum test duration 2.0ms, one output loaded at a time and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5. ©1989 Fairchild Semiconductor Corporation 74AC520, 74ACT520 Rev. 1.4 = +25° (V) Conditions Typ. ...

Page 6

... I Maximum Quiescent CC Supply Current I Maximum Quiescent CC Supply Current Notes: 5. All outputs loaded; thresholds on input associated with output under test. 6. Maximum test duration 2.0ms, one output loaded at a time. ©1989 Fairchild Semiconductor Corporation 74AC520, 74ACT520 Rev. 1 (V) Conditions Typ 0. 4.5 V 1.5 OUT CC – ...

Page 7

... Propagation Delay, PLH Propagation Delay, PHL Note: 8. Voltage range 5.0 is 5.0V ± 0.5V Capacitance Symbol Parameter C Input Capacitance IN C Power Dissipation Capacitance PD ©1989 Fairchild Semiconductor Corporation 74AC520, 74ACT520 Rev. 1.4 = +25° 50pF C L (7) V (V) Min. Typ. Max. CC 3.3 4.0 7.5 11.5 5.0 2.5 5.5 8.5 3.3 4.5 8.0 12 ...

Page 8

... Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide ©1989 Fairchild Semiconductor Corporation 74AC520, 74ACT520 Rev. 1.4 Package Number M20B 8 www.fairchildsemi.com ...

Page 9

... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide ©1989 Fairchild Semiconductor Corporation 74AC520, 74ACT520 Rev. 1.4 Package Number M20D 9 www.fairchildsemi.com ...

Page 10

... Physical Dimensions (Continued) Dimensions are in inches (millimeters) unless otherwise noted. Figure 3. 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide ©1989 Fairchild Semiconductor Corporation 74AC520, 74ACT520 Rev. 1.4 Package Number N20A 10 www.fairchildsemi.com ...

Page 11

... Definition of Terms Datasheet Identification Product Status Advance Information Formative or In Design Preliminary First Production No Identification Needed Full Production Obsolete Not In Production ©1989 Fairchild Semiconductor Corporation 74AC520, 74ACT520 Rev. 1.4 HiSeC Programmable Active Droop ® QFET i-Lo QS ImpliedDisconnect QT Optoelectronics IntelliMAX Quiet Series ISOPLANAR RapidConfigure ...

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