72V82L15PA IDT, 72V82L15PA Datasheet - Page 7

• Manufacturer Part Number: 72V82L15PA
• Description: FIFO 1Kx9 ASYNCHRONOUS DUAL FIFO 3.3V
• Manufacturer: IDT

Specifications of 72V82L15PA

• Number Of Circuits: 2
• Data Bus Width: 9 bit
• Bus Direction: Unidirectional
• Memory Size: 18 KB
• Timing Type: Asynchronous
• Organization: 1 K x 9 x 2
• Access Time: 15 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V
• Maximum Operating Current: 100 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TSSOP-56
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Part # Aliases: IDT72V82L15PA

OPERATING MODES:
system (i.e. FF is monitored on the device where W is used; EF is monitored on
the device where R is used).
Single Device Mode
application requirements are for 512/1,024/2,048/4,096/8,192 words or less.
These FIFOs are in a Single Device Configuration when the Expansion In (XI)
control input is grounded (see Figure 12).
Depth Expansion
are for greater than 512/1,024/2,048/4,096/8,192 words. Figure 14 demon-
HF
XO
IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
R
W
XI
W
W
R
R
Care must be taken to assure that the appropriate flag is monitored by each
A single IDT72V81/72V82/72V83/72V84/72V85 may be used when the
These devices can easily be adapted to applications when the requirements
t
XIS
HALF-FULL OR LESS
LAST PHYSICAL
LOCATION
WRITE TO
t
XOL
t
XI
FIRST PHYSICAL
LOCATION
WRITE TO
t
WHF
t
XOH
t
XIR
Figure 9. Half-Full Flag Timing
Figure 10. Expansion Out
Figure 11. Expansion In
MORE THAN HALF-FULL
7
strates a four-FIFO Depth Expansion using two IDT72V81/72V82/72V83/
72V84/72V85s. Any depth can be attained by adding additional IDT72V81/
72V82/72V83/72V84/72V85s. These FIFOs operate in the Depth Expansion
mode when the following conditions are met:
1. The first FIFO must be designated by grounding the First Load (FL) control
2. All other FIFOs must have FL in the high state.
3. The Expansion Out (XO) pin of each device must be tied to the Expansion
4. External logic is needed to generate a composite Full Flag (FF) and Empty
5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in
t
input.
In (XI) pin of the next device. See Figure 14.
Flag (EF). This requires the ORing of all EFs and ORing of all FFs (i.e. all
must be set to generate the correct composite FF or EF). See Figure 14.
the Depth Expansion Mode.
XIS
LAST PHYSICAL
READ FROM
LOCATION
t
XOL
FIRST PHYSICAL
READ FROM
LOCATION
t
RHF
COMMERCIAL AND INDUSTRIAL
t
XOH
TEMPERATURE RANGES
HALF-FULL OR LESS
3966 drw 11
3966 drw 12
3966 drw 13