831721AGILF IDT, 831721AGILF Datasheet - Page 9

• Manufacturer Part Number: 831721AGILF
• Description: Clock Drivers & Distribution
• Manufacturer: IDT

Specifications of 831721AGILF

• Product Category: Clock Drivers & Distribution
• Rohs: yes
• Part # Aliases: ICS831721AGILF

ICS831721I Data Sheet
Applications Information
Recommendations for Unused Input Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pullups and pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to ground.
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage V
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the V
swing. For example, if the input clock swing is 2.5V and V
R1 and R2 value should be adjusted to set V
below are for when both the single ended swing and V
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
ICS831721AGI REVISION A AUGUST 19, 2011
REF
in the center of the input voltage
REF
= V
REF
CC
at 1.25V. The values
/2 is generated by
CC
CC
are at the
= 3.3V,
9
line impedance. For most 50 applications, R3 and R4 can be 100 .
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however V
than -0.3V and V
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
IH
cannot be more than V
DIFFERENTIAL CLOCK/DATA MULTIPLEXER
©2011 Integrated Device Technology, Inc.
CC
+ 0.3V. Though some
IL
cannot be less