74LCX162373MTDX Fairchild Semiconductor, 74LCX162373MTDX Datasheet - Page 3

• Manufacturer Part Number: 74LCX162373MTDX
• Description: IC LATCH TRANSP 16BIT LV 48TSSOP
• Manufacturer: Fairchild Semiconductor
• Series: 74LCXr
• Type: D-Typer

Specifications of 74LCX162373MTDX

• Logic Type: D-Type Transparent Latch
• Circuit: 8:8
• Output Type: Tri-State
• Voltage - Supply: 2 V ~ 3.6 V
• Independent Circuits: 2
• Delay Time - Propagation: 1.5ns
• Current - Output High, Low: 12mA, 12mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Logic Family: LCX
• Number Of Bits: 16
• Number Of Elements: 2
• Latch Mode: Transparent
• Polarity: Non-Inverting
• Technology: CMOS
• Package Type: TSSOP W
• Propagation Delay Time: 9ns
• Operating Supply Voltage (typ): 2.5/3.3V
• High Level Output Current: -12mA
• Low Level Output Current: 12mA
• Operating Supply Voltage (min): 2V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
The LCX162373 contains sixteen D-type latches with
3-STATE standard outputs. The device is byte controlled
with each byte functioning identically, but independent of
the other. Control pins can be shorted together to obtain full
16-bit operation. The following description applies to each
byte. When the Latch Enable (LE
the I
transparent, i.e. a latch output will change state each time
Logic Diagrams
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
n
enters the latches. In this condition the latches are
n
) input is HIGH, data on
3
its I input changes. When LE
information that was present on the I inputs a setup time
preceding the HIGH-to-LOW transition of LE
3-STATE standard outputs are controlled by the Output
Enable (OE
puts are in the 2-state mode. When OE
dard outputs are in the high impedance mode but this does
not interfere with entering new data into the latches.
n
) input. When OE
n
n
is LOW, the latches store
is LOW, the standard out-
n
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is HIGH, the stan-
n
. The