MT47H128M8HQ-37EL MICRON [Micron Technology], MT47H128M8HQ-37EL Datasheet - Page 124
MT47H128M8HQ-37EL
Manufacturer Part Number
MT47H128M8HQ-37EL
Description
DDR2 SDRAM
Manufacturer
MICRON [Micron Technology]
Datasheet
1.MT47H128M8HQ-37EL.pdf
(131 pages)
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Figure 79: RESET Function
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
Bank address
Command
Address
ODT
DQS 3
DM 3
CK#
CKE
A10
DQ 3
R
CK
TT
Bank a
READ
Col n
T0
High-Z
High-Z
Notes:
NOP 2
T1
1. V
2. Either NOP or DESELECT command may be applied.
3. DM represents DM for x4/x8 configuration and UDM, LDM for x16 configuration. DQS
4. In certain cases where a READ cycle is interrupted, CKE going HIGH may result in the
5. Initialization timing is shown in Figure 42 (page 85).
represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, and RDQS# for the appropri-
ate configuration (x4, x8, x16).
completion of the burst.
DD
Bank b
Col n
READ
, V
T2
DDL
, V
DDQ
NOP 2
Indicates a break in
time scale
T3
, V
DO
TT
, and V
DO
NOP 2
T4
124
System
DO
RESET
REF
must be valid at all times.
t DELAY
Unknown
T5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1
1Gb: x4, x8, x16 DDR2 SDRAM
R
TT
On
High-Z
High-Z
Transitioning Data
t CL
© 2004 Micron Technology, Inc. All rights reserved.
t CK
Start of normal 5
initialization
t CL
sequence
NOP 2
Ta0
4
T = 400ns (MIN)
t CKE (MIN)
All banks
Tb0
PRE
Don’t Care
High-Z
t RPA
Reset
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