AM186ES-20VC/W AMD [Advanced Micro Devices], AM186ES-20VC/W Datasheet - Page 50

• Manufacturer Part Number: AM186ES-20VC/W
• Description: High Performance, 80C186-/80C188-Compatible and 80L186-/80L188-Compatible, 16-Bit Embedded Microcontrollers
• Manufacturer: AMD [Advanced Micro Devices]

DMA Channel Control Registers
Each DMA control register determines the mode of op-
eration for the particular DMA channel. The DMA con-
trol registers specify the following:
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The mode of synchronization
Whether bytes or words are transferred
Whether an interrupt is generated after the last
transfer
Whether the DRQ pins are configured as INT pins
Whether DMA activity ceases after a programmed
number of DMA cycles
The relative priority of the DMA channel with re-
spect to the other DMA channel
Whether the source address is incremented, decre-
mented, or maintained constant after each transfer
Whether the source address addresses memory or
I/O space
Whether the destination address is incremented,
decremented, or maintained constant after trans-
fers
Whether the destination address addresses mem-
ory or I/O space
Destination Address Ch. 1
Destination Address Ch. 0
20-bit Adder/Subtractor
Transfer Counter Ch. 1
Transfer Counter Ch. 0
Source Address Ch. 1
Source Address Ch. 0
Am186/188ES and Am186/188ESLV Microcontrollers
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Figure 10. DMA Unit Block Diagram
Internal Address/Data Bus
P R E L I M I N A R Y
Channel Control Register 1
Channel Control Register 0
Adder Control
Control
Logic
DMA
DMA Priority
The DMA channels can be programmed so that one
channel is always given priority over the other, or they
can be programmed to alternate cycles when both
have DMA requests pending. DMA cycles always have
priority over internal CPU cycles except between
locked memory accesses or word accesses to odd
memory locations. However, an external bus hold
takes priority over an internal DMA cycle.
Because an interrupt request cannot suspend a DMA
operation and the CPU cannot access memory during
a DMA cycle, interrupt latency time suffers during se-
quences of continuous DMA cycles. An NMI request,
however, causes all internal DMA activity to halt. This
allows the CPU to respond quickly to the NMI request.
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Logic
Timer Request
Selection
Request
Logic
Interrupt
Request
DRQ1/Serial Port
DRQ0/Serial Port