ts32mss64v8l2 Transcend Information. Inc., ts32mss64v8l2 Datasheet - Page 10

• Manufacturer Part Number: ts32mss64v8l2
• Description: 256mb 144pin Pc100 Cl2 Sdram Dimm With 16m X 8 3.3volt
• Manufacturer: Transcend Information. Inc.

TS32MSS64V8L2
Transcend information Inc
SIMPLIFIED TRUTH TABLE
Register
Refresh
Bank Active & Row Addr.
Read &
Column
Address
Write &
Column
Address
Burst Stop
Precharge
Clock
Suspend or
Active Power
Down
Precharge
Power
Down Mode
DQM
No Operation Command
Note: 1. OP Code : Operand Code
2. MRS can be issued only at all banks precharge state.
3. Auto refresh functions are as same as CBR refresh of DRAM.
4. BA
5. During burst read or write with auto precharge, new read/write command can not be issued.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
A
A new command can be issued after 2 CLK cycles of MRS.
The automatical precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at all banks precharge state.
If both BA
If both BA
If both BA
If both BA
If A
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
0
~A
0
10
~BA
COMMAND
Mode Register Set
Auto Refresh
Self
Refresh
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Bank Selection
Both Banks
Entry
Exit
Entry
Exit
11
/AP is “High” at row precharge, BA
, BA
1
: Bank select address.
0
0
0
0
and BA
and BA
0
is “Low” and BA
is “High” and BA
~BA
Entry
Exit
1
: Program keys. (@MRS)
1
1
are “Low” at read, write, row active and precharge, bank A is selected.
are “High” at read, write, row active and precharge, bank D is selected.
1
1
is “High” at read, write, row active and precharge, bank B is selected.
is “Low” at read, write, row active and precharge, bank C is selected.
CKEn-1 CKEn
H
H
H
H
H
H
H
H
H
H
H
L
L
L
0
and BA
H
H
X
H
H
X
L
X
X
X
X
L
L
X
1
are ignored and all banks are selected.
/CS
H
H
X
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
/RAS
H
X
H
H
H
X
V
X
X
H
X
V
X
X
H
L
L
L
L
10
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
/CAS
H
X
H
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
/WE
H
H
X
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
144PIN PC100 Unbuffered SO-DIMM
DQM
X
X
X
X
X
X
X
X
X
X
X
X
V
X
BA
256MB With 16M X 8 CL2
V
V
V
V
X
0,1
OP CODE
A
10
H
H
H
L
L
L
Row Address
/AP
X
X
X
X
X
X
X
A
Address
(A0~A8)
Address
(A0~A8)
11
Column
Column
, A
X
0
~A
9
Note
4, 5
4, 5
1,2
3
3
3
3
4
4
6
7