PCA9513 Philips Semiconductors (Acquired by NXP), PCA9513 Datasheet - Page 6

• Manufacturer Part Number: PCA9513
• Description: Hot Swappable I2C And Smbus Bus Bufferthe PCA9513 And PCA9514 Are Hot Swappable i C And Smbus Buffers That Allows I/o Card Insertion Into a Live Backplane Without Corrupting The Data And Clock Buses. Control Circuitry Prevents The Backplane From Bein
• Manufacturer: Philips Semiconductors (Acquired by NXP)

Philips Semiconductors
OPERATION
Start-up
An under voltage/initialization circuit holds the parts in a
disconnected state which presents high impedance to all SDA and
SCL pins during power-up. A low on the enable pin also forces the
parts into the low current disconnected state when the I
essentially zero. As the power supply is brought up and the enable
is high or the part is powered and the enable is taken from low to
high it enters an initialization state where the internal references are
stabilized. The 92 µA input pull-ups on PCA9513 are also enabled in
the initialization state. At the end of the initialization state the “Stop
Bit And Bus Idle” detect circuit is enabled. With the enable pin high
long enough to complete the initialization state and remaining high
when all the SDA and SCl pins have been high for the bus idle time
or when all pins are high and a stop condition is seen on the SDAIN
and SCLIN pins, SDAIN is connected to SDAOUT and SCLIN is
connected to SCLOUT.
A 92 µA pull-up current source on SDAIN and SCLIN of PCA9513 is
activated during the initialization state and remain active until the
power is removed or the enable is taken low. When the 92 µA
pull-up is active it will become high impedance any time the pin
voltage is greater than V
pin up to V
Connect Circuitry
Once the connection circuitry is activated, the behavior of SDAIN
and SDAOUT as well as SCLIN and SCLOUT become identical with
each acting as a bidirectional buffer that isolates the input
capacitance from the output bus capacitance while communicating
the logic levels. A low forced on either SDAIN or SDAOUT will
cause the other pin to be driven to a low by the part. The same is
also true for the SCL pins. Noise between 0.7V
generally ignored because a falling edge is only recognized when it
falls below 0.7V
falling edge is seen on one pin the other pin in the pair turns on a
pull down driver that is referenced to a small voltage above the
falling pin. The driver will pull the pin down at a slew rate determined
by the driver and the load initially, because it does not start until the
first falling pin is below 0.7V
or slow slew rate, if it is faster than the pull down slew rate then the
initial pull down rate will continue. If the first falling pin has a slow
slew rate then the second pin will be pulled down at its initial slew
rate only until it is just above the first pin voltage the they will both
continue down at the slew rate of the first.
Once both sides are low they will remain low until all the external
drivers have stopped driving lows. If both sides are being driven low
to the same value for instance, 10 mV by external drivers, which is
the case for clock stretching and is typically the case for
acknowledge, and one side external driver stops driving that pin will
rise and rise above the nominal offset voltage until the internal driver
catches up and pulls it back down to the offset voltage. This bounce
is worst for low capacitances and low resistances, and may become
2004 Jan 07
Hot swappable I
CC
.
CC
with a slew rate of at least 1.25 V/µs. When a
CC
, otherwise it provides current to pull the
CC
. The first falling pin may have a fast
2
C and SMBus bus buffer
CC
and V
CC
CC
is
is
6
excessive. When the last external driver stops driving a low, that pin
will bounce up and settle out just above the other pin as both rise
together with a slew rate determined by the internal slew rate control
and the RC time constant. As long as the slew rate is at least
1.25 V/µs, when the pin voltage exceeds 0.8 V for PCA9513 and
PCA9514, rise time accelerators circuits are turned on and the pull
down driver is turned off.
Propagation Delays
The delay for a rising edge is determined by the combined pull-up
current from the bus resistors and the rise time accelerator current
source and the effective capacitance on the lines. If the pull-up
currents are the same, any difference in rise time is directly
proportional to the difference in capacitance between the two sides.
The t
input capacitance and would be positive if the output capacitance is
larger than the input capacitance, when the currents are the same.
The t
fall until the input is below 0.7V
zero delay, and the output has a limited maximum slew rate, and
even if the input slew rate is slow enough that the output catches up
it will still lag the falling voltage of the input by the offset voltage. The
maximum t
and the output is still limited by its turn on delay and the falling edge
slew rate. The output falling edge slew rate is a function of the
internal maximum slew rate which is a function of temperature, V
and process, as well as the load current and the load capacitance.
Rise Time Accelerators
During positive bus transitions a 2 mA current source is switched on
to quickly slew the SDA and SCL lines high once the input level of
0.8 for the PCA9513 and PCA9514 are exceeded. The rising edge
rate should be at least 1.25 V/µs to guarantee turn on of the
accelerators. The 0.8 V threshold of PCA9513 and PCA9514 allows
for larger bounce-or-noise without falsely triggering the rise time
accelerators.
READY Digital Output
This pin provides a digital flag which is low when either ENABLE is
low or the start-up sequence described earlier in this section has not
been completed. READY goes high when ENABLE is high and
start-up is complete. The pin is driven by an open drain pull-down
capable of sinking 3 mA while holding 0.4 V on the pin. Connect a
resistor of 10 k to V
ENABLE Low Current Disable
Grounding the ENABLE pin disconnects the backplane side from the
card side, disables the rise-time accelerators, drives READY low,
disables the bus precharge circuitry, and puts the part in a low
current state. When the pin voltage is driven all the way to V
part waits for data transactions on both the backplane and card
sides to be complete before reconnecting the two sides.
PLH
PHL
may be negative if the output capacitance is less than the
can never be negative because the output does not start to
PHL
occurs when the input is driven low with zero delay
CC
to provide the pull-up.
PCA9513; PCA9514
CC
, and the output turn on has a non
Product data
CC
, the
CC
,