fs6370 AMI Semiconductor, Inc., fs6370 Datasheet - Page 7

• Manufacturer Part Number: fs6370
• Description: Fs6370-01g Eeprom Programmable 3-pll Clock Generator Ic
• Manufacturer: AMI Semiconductor, Inc.

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F F S S 6 6 3 3 7 7 0 0 - - 0 0 1 1 / / F F S S 6 6 3 3 7 7 0 0 - - 0 0 1 1 g g E E E E P P R R O O M M P P r r o o g g r r a a m m m m a a b b l l e e 3 3 - - P P L L L L C C l l o o c c k k G G e e n n e e r r a a t t o o r r I I C C
A A M M I I S S e e m m i i c c o o n n d d u u c c t t o o r r - - R R e e v v . . 2 2 . . 0 0 , , M M a a r r . . 0 0 5 5
6.1.1 Write Operation
The EEPROM can only be written to with the random register write procedure (see Section 8.2.2). The procedure consists of the device address, the
register address, a R/W bit, and one byte of data.
Following the STOP condition, the EEPROM initiates its internally timed 4ms write cycle, and commits the data byte to memory. No acknowledge signals
are generated during the EEPROM internal write cycle.
If a stop bit is transmitted before the entire write command sequence is complete, then the command is aborted and no data is written to memory.
If more than eight bits are transmitted before the stop bit is sent, then the EEPROM will clear the previously loaded data byte and will begin loading the
data buffer again.
6.1.2 Acknowledge Polling
The EEPROM does not acknowledge while it internally commits data to memory. This feature can be used to increase data throughput by determining
when the internal write cycle is complete.
The process is to initiate the random register write procedure with a START condition, the EEPROM device address, and the write command bit (R/W=0).
If the EEPROM has completed its internal 4ms write cycle, the EEPROM will acknowledge on the next clock, and the write command can continue.
If the EEPROM has not completed the internal 4ms write cycle, the random register write procedure must be restarted by sending the START condition,
device address and R/W bit. This sequence must be repeated until the EEPROM acknowledges.
6.1.3 Read Operation
The EEPROM supports both the random register read procedure and the sequential register read procedure (both are outlined in Section 6).
For sequential read operations, the EEPROM has an internal address pointer that increments by one at the end of each read operation. The pointer directs
the EEPROM to transmit the next sequentially addressed data byte, allowing the entire memory contents to be read in one operation.
6 6 . . 2 2 D D i i r r e e c c t t R R e e g g i i s s t t e e r r P P r r o o g g r r a a m m m m i i n n g g
The FS6370 control registers may be directly accessed by simply using the FS6370 device address in the read or write operations. The operation of the
device will follow the register values. The register map of the FS6370 is identical to that of the EEPROM shown in Table 3.
The FS6370 supports the random read and write procedures, as well as the sequential read and write procedures described in Section 8.
The device address for the FS6370 is:
7.0 Cost Reduction Migration Path
The FS6370 is compatible with the programmable register-based FS6377 or a fixed-frequency ROM-based clock generator. Attention should be paid to
the board layout if a migration path to either of these devices is desired.
7 7 . . 1 1 P P r r o o g g r r a a m m m m i i n n g g M M i i g g r r a a t t i i o o n n P P a a t t h h
If the design can support I
Figure 5 shows the five pins that may not be compatible between the various devices if programming of the FS6370 or the FS6377 is desired.
A A 6 6
1
A A 5 5
0
2
C programming overhead, a cost reduction from the EEPROM-based FS6370 to the register-based FS6377 is possible.
A A 4 4
1
A A 3 3
1
A A 2 2
1
A A 1 1
0
7
A A 0 0
0
Data Sheet