MAX1265 Maxim, MAX1265 Datasheet - Page 11

• Manufacturer Part Number: MAX1265
• Description: 265ksps / +3V / 6-/2-Channel / 12-Bit ADCs with +2.5V Reference and Parallel Interface
• Manufacturer: Maxim

Together with the input impedance, this capacitor
forms an RC filter, limiting the ADC’s signal bandwidth.
The MAX1265/MAX1267 T/H stage offers a 250kHz full-
linear and a 3MHz full-power bandwidth. This makes it
possible to digitize high-speed transients and measure
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid high-frequency signals being aliased into the fre-
quency band of interest, anti-alias filtering is recom-
mended.
Initiate a conversion by writing a control byte that selects
the multiplexer channel and configures the MAX1265/
MAX1267 for either unipolar or bipolar operation. A
write pulse (WR + CS) can either start an acquisition
interval or initiate a combined acquisition plus conver-
sion. The sampling interval occurs at the end of the
acquisition interval. The acquisition mode (ACQMOD)
bit in the input control byte (Table 1) offers two options
Figure 4. Conversion Timing Using Internal Acquisition Mode
CS
WR
D11–D0
RD
INT
DOUT
t
with +2.5V Reference and Parallel Interface
CSWS
HIGH-Z
______________________________________________________________________________________
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
t
DS
t
WR
Starting a Conversion
t
CS
ACQMOD = 0
CONTROL
BYTE
Input Bandwidth
t
ACQ
t
DH
t
CSWH
t
CONV
t
INT1
t
D0
for acquiring the signal: an internal and an external
acquisition. The conversion period lasts for 13 clock
cycles in either the internal or external clock or acquisi-
tion mode. Writing a new control byte during a conver-
sion cycle aborts the conversion and starts a new
acquisition interval.
Select internal acquisition by writing the control byte
with the ACQMOD bit cleared (ACQMOD = 0). This
causes the write pulse to initiate an acquisition interval
whose duration is internally timed. Conversion starts
when this acquisition interval (three external clock
cycles or approximately 1µs in internal clock mode)
ends (Figure 4). Note that, when the internal acquisition
is combined with the internal clock, the aperture jitter
can be as high as 200ps. Internal clock users wishing
to achieve the 50ps jitter specification should always
use external acquisition mode.
VALID DATA
t
TR
Internal Acquisition
HIGH-Z
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