AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 47

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AT32UC3A3128

Manufacturer Part Number
AT32UC3A3128
Description
Manufacturer
Atmel Corporation

Specifications of AT32UC3A3128

Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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11
5.3
5.3.1
5.3.2
32000D–04/2011
Operation of the MMU and MMU exceptions
The tlbw instruction
TLB synonyms
The MMU uses both hardware and software mechanisms in order to perform its memory remap-
ping operations. The following tasks are performed by hardware:
The following tasks must be performed by software:
The tlbw instruction is implemented in order to aid in performing TLB maintenance. The instruc-
tion copies the contents of TLBEHI and TLBELO into the TLB entry pointed to by the ITLB or
DTLB Replacement Pointers (IRP/DRP) in the MMU Control Register. The TLBEHI[I] bit decides
if the ITLB or the DTLB should be addressed. IRP and DRP may in some implementations be
automatically updated by hardware in order to implement a TLB replacement algorithm in hard-
ware. Software may update them before executing tlbw in order to implement a software
replacement algorithm.
In some implementations, the TLB data structures may be mapped into the P4 space. In such
implementations, the TLB data structures may be updated with regular memory access
instructions.
Implementations using virtually indexed caches may be subject to cache inconsistencies,
depending on the page size used and number of lines in the cache. These inconsistencies may
occur when multiple virtual addresses are mapped to the same physical address, since a trans-
lated part of VPN may be used to index the cache. This implies that the same physical address
may be mapped to different cache lines, causing cache inconsistency.
Synonym problems can only appear when addressing data residing in a virtually indexed cache.
Addressing uncached memory or accessing untranslated memory will never cause synonym
problems.
It is the responsability of the OS to define a policy ensuring that no synonym problems may
arise. No hardware support is provided to avoid TLB synonyms.
1. The MMU decodes the virtual address and tries to find a matching entry in the TLB.
2. The matching entry is used to determine whether the access has the appropriate
3. If any other event arises that requires software intervention, an appropriate exception is
4. If the correct entry was found in the TLB, and the access permissions were not violated,
1. Setup of the MMU hardware by initializing the MMU-related registers and data struc-
2. Maintenance of the TLB structure. TLB entries are written, invalidated and replaced by
3. The MMU may generate several exceptions. Software exception handlers must be writ-
This entry is used to generate a physical address. If no matching entry is found, a TLB
miss exception is issued.
access rights, cacheability, bufferability and so on. If the access is not permitted, a TLB
Protection Violation exception is issued.
issued.
the memory access is performed without any further software intervention.
tures if needed.
means of software. A tlbw instruction is included in the instruction set to support this.
ten in order to service these exceptions.
AVR32
47

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