AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 145

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AT32UC3A3128

Manufacturer Part Number
AT32UC3A3128
Description
Manufacturer
Atmel Corporation

Specifications of AT32UC3A3128

Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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11
If the on chip debug system is enabled, this instruction traps a software breakpoint for debugging. The breakpoint instruc-
tion will enter debug mode disabling all interrupts and exceptions. If the on chip debug system is not enabled, this
instruction will execute as a nop.
If no on chip debug system is implemented, this instruction will execute as a "NOP".
32000D–04/2011
BREAKPOINT – Software Debug Breakpoint
Architecture revision:
Architecture revision1 and higher.
Description
Operation:
I.
Syntax:
I.
Operands:
Status Flags:
Opcode:
Note:
15
1
if (SR[DM]==0)
else
breakpoint
None
Q:
V:
N:
Z:
C:
1
0
RSR_DBG ← SR;
RAR_DBG ← address of first non-completed instruction;
SR[R] ← 1;
SR[J] ← 1;
SR[D] ← 1;
SR[M2:M0] ← B’110;
SR[DM] ← 1;
SR[EM] ← 1;
SR[GM] ← 1;
PC ← EVBA+0x1C;
PC ← PC + 2;
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
1
0
1
9
1
8
0
0
1
1
4
1
3
0
0
AVR32
1
0
1
145

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