AT32UC3A1256 Atmel Corporation, AT32UC3A1256 Datasheet - Page 430
AT32UC3A1256
Manufacturer Part Number
AT32UC3A1256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
Specifications of AT32UC3A1256
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
69
Ext Interrupts
69
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A1256-U
Manufacturer:
ATMEL
Quantity:
496
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A0128 PDF datasheet #4
- AT32UC3A0128 PDF datasheet #5
- Current page: 430 of 826
- Download datasheet (11Mb)
32058K AVR32-01/12
28.8.5
Register Name:
Access Type:
Reset Value:
•
•
PASR parameter is transmitted to the SDRAM during initialization to specify whether only one quarter, one half or all banks
of the SDRAM array are enabled. Disabled banks are not refreshed in self-refresh mode. This parameter must be set
according to the SDRAM device specification.
After initialization, as soon as PASR field is modified and self-refresh mode is activated, the Extended Mode Register is
accessed automatically and PASR bits are updated before entry in self-refresh mode.
•
TCSR parameter is transmitted to the SDRAM during initialization to set the refresh interval during self-refresh mode
depending on the temperature of the low-power SDRAM. This parameter must be set according to the SDRAM device
specification.
After initialization, as soon as TCSR field is modified and self-refresh mode is activated, the Extended Mode Register is
accessed automatically and TCSR bits are updated before entry in self-refresh mode.
•
DS parameter is transmitted to the SDRAM during initialization to select the SDRAM strength of data output. This parame-
ter must be set according to the SDRAM device specification.
00
01
10
11
LPCB: Low-power Configuration Bits
PASR: Partial Array Self-refresh (only for low-power SDRAM)
TCSR: Temperature Compensated Self-Refresh (only for low-power SDRAM)
DS: Drive Strength (only for low-power SDRAM)
31
23
15
–
–
–
7
–
SDRAMC Low Power Register
Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to
the SDRAM device.
The SDRAM Controller issues a Self-refresh command to the SDRAM device, the SDCLK clock is
deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when
accessed and enters it after the access.
The SDRAM Controller issues a Power-down Command to the SDRAM device after each access, the
SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and
enters it after the access.
The SDRAM Controller issues a Deep Power-down command to the SDRAM device. This mode is
unique to low-power SDRAM.
30
22
14
–
–
–
6
PASR
29
21
13
–
–
5
TIMEOUT
LPR
Read/Write
0x0
28
20
12
–
–
4
27
19
11
–
–
3
–
DS
26
18
10
–
–
2
–
25
17
–
–
9
1
AT32UC3A
TCSR
LPCB
24
16
–
–
8
0
430
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