E28F128J3A150 Intel Corporation, E28F128J3A150 Datasheet
E28F128J3A150
Available stocks
Related parts for E28F128J3A150
E28F128J3A150 Summary of contents
Page 1
Intel StrataFlash 28F256J3, 28F128J3, 28F640J3, 28F320J3 (x8/x16) Product Features Performance — 110/115/120/150 ns Initial Access Speed — 125 ns Initial Access Speed (256 Mbit density only) — Asynchronous Page-Mode Reads — Asynchronous Page-Mode Reads (256Mbit density ...
Page 2
... Intel's website at http://www.intel.com. Copyright © 2004, Intel Corporation. All rights reserved. Intel and ETOX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. ...
Page 3
Contents 1.0 Introduction....................................................................................................................................7 1.1 Document Purpose ...............................................................................................................7 1.2 Nomenclature .......................................................................................................................7 1.3 Conventions..........................................................................................................................7 2.0 Device Description ........................................................................................................................8 2.1 Product Overview .................................................................................................................8 2.2 Ballout Diagrams ..................................................................................................................9 2.3 Signal Descriptions .............................................................................................................12 2.4 Block Diagram ....................................................................................................................13 2.5 Memory Map .......................................................................................................................14 3.0 Device Operations .......................................................................................................................15 ...
Page 4
Contents 8.0 Special Modes.............................................................................................................................. 30 8.1 Set Read Configuration Register Command ...................................................................... 30 8.2 Status (STS) ....................................................................................................................... 30 9.0 Power and Reset.......................................................................................................................... 32 9.1 Power-Up/Down Characteristics......................................................................................... 32 9.2 Power Supply Decoupling................................................................................................... 32 9.3 Reset Characteristics.......................................................................................................... 32 10.0 Electrical Specifications ............................................................................................................. ...
Page 5
Revision History Date of Version Revision 07/07/99 -001 08/03/99 -002 09/07/99 -003 12/16/99 -004 03/16/00 -005 06/26/00 -006 2/15/01 -007 04/13/01 -008 Datasheet Description Original Version A –A indicated on block diagram 0 2 Changed Minimum Block Erase time,I OL ...
Page 6
Contents Date of Version Revision 07/27/01 -009 10/31/01 -010 03/21/02 -011 12/12/02 -012 01/24/03 -013 12/09/03 -014 1/3/04 -015 1/23/04 -016 1/23/04 -016 5/19/04 -018 6 Description ® Added Figure 4, 3 Volt Intel StrataFlash ® Added Figure 5, 3 ...
Page 7
Introduction This document contains information pertaining to the Intel StrataFlash purpose of this document is to facilitate the use of this product and describe the features, operations, and specifications of this device. 1.1 Nomenclature AMIN: AMIN = A0 for ...
Page 8
Functional Overview The Intel StrataFlash 16Mwords (256-Mbit, available on the 0.18µm lithography process only), 16 Mbytes or 8 Mwords (128-Mbit), 8 Mbytes or 4 Mwords (64-Mbit), and 4 Mbytes or 2 Mwords (32-Mbit). These devices ...
Page 9
Additionally, the configuration command allows the STS signal to be configured to pulse on completion of programming and/or block erases. Three CE signals are ...
Page 10
Memory Map Figure 2. Intel StrataFlash A[24-0]: 256 Mbit A [23-0]:128 Mbit A [22-0]: 64 Mbit A [21-0]: 32 Mbit 1FFFFFF 128-Kbyte Block 1FE0000 0FFFFFF 128-Kbyte Block 0FE0000 07FFFFF 128-Kbyte Block 07E0000 03FFFFF 128-Kbyte Block ...
Page 11
Package Information 3.1 56-Lead TSOP Package Figure 3. 56-Lead TSOP Package Drawing and Specifications Z Pin 1 See Detail A Detail A Table 1. 56-Lead TSOP Dimension Table Sym Package Height A Standoff A 1 Package Body Thickness A ...
Page 12
Easy BGA (J3) Package Figure 4. Intel StrataFlash Ball A1 Corner Top View - Ball side down A1 A2 Table ...
Page 13
VF-BGA (J3) Package Figure 5. Intel StrataFlash ...
Page 14
Ballout and Signal Descriptions ® Intel StrataFlash memory is available in three package types. Each density of the J3C is supported on both 64-ball Easy BGA and 56-lead Thin Small Outline Package (TSOP) packages. A ...
Page 15
TSOP (32/64/128/256 Mbit) Figure 7. Intel StrataFlash 28F160S3 28F320J5 RP# ...
Page 16
Signal Descriptions Table 3 describes active signals used. Table 3. Signal Descriptions (Sheet Symbol Type BYTE-SELECT ADDRESS: Selects between high and low byte when the device mode. A0 Input ...
Page 17
Table 3. Signal Descriptions (Sheet Symbol Type GND Supply GROUND: Do not float any ground signals. NC — NO CONNECT: Lead is not internally connected; it may be driven or floated. RESERVED for FUTURE USE: Balls designated ...
Page 18
Maximum Ratings and Operating Conditions 5.1 Absolute Maximum Ratings This datasheet contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you ...
Page 19
Electrical Specifications 6.1 DC Current Characteristics Table 6. DC Current Characteristics Symbol Parameter I Input and V Load Current LI PEN I Output Leakage Current Standby Current CCS Power-Down Current CCD CC I ...
Page 20
DC Voltage Characteristics Table 7. DC Voltage Characteristics Symbol V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH V Lockout during Program, PEN V ...
Page 21
AC Characteristics 7.1 Read Operations Table 8. Read Operations (Sheet Asynchronous Specifications (All units in ns unless otherwise noted) # Sym Parameter Density 32 Mbit 64 Mbit Read/Write R1 t AVAV Cycle Time 128 Mbit 256 ...
Page 22
Table 8. Read Operations (Sheet Asynchronous Specifications (All units in ns unless otherwise noted) # Sym Parameter Density t FLQV/ R12 BYTE# to Output Delay t FHQV R13 t BYTE# to Output in ...
Page 23
NOTES low is defined as the last edge of CE0, CE1, or CE2 that enables the device first edge of CE0, CE1, or CE2 that disables the device (see 2. When reading the flash array a ...
Page 24
Write Operations Table 9. Write Operations Versions # Symbol RP# High Recovery to WE# (CE PHWL PHEL (WE#) Low to WE# (CE ELWL WLEL X W3 ...
Page 25
Block Erase, Program, and Lock-Bit Configuration Performance Table 10. Configuration Performance # Sym Write Buffer Byte Program Time W16 (Time to Program 32 bytes/16 words) t WHQV3 W16 Byte Program Time (Using Word/Byte Program Command) t EHQV3 Block Program ...
Page 26
Figure 11. Asynchronous Write Waveform ADDRESS [A] CEx (WE#) [E (W)] W2 WE# (CEx) [W (E)] OE# [G] DATA [D/Q] STS[R] W1 RP# [P] VPEN [V] Figure 12. Asynchronous Write to Read Waveform Address [A] CE# ...
Page 27
Reset Operation Figure 13. AC Waveform for Reset Operation NOTE: STS is shown in its ...
Page 28
Figure 15. Transient Equivalent Testing Load Circuit NOTE: C Includes Jig Capacitance. L Test Configuration 2.7 V 3.6 V CCQ CC 7.6 Capacitance T = +25 ° MHz A ...
Page 29
Power and Reset Specifications This section provides an overview of some system level considerations in regards to the flash device. This section provides a brief description of power-up, power-down, decoupling and reset design considerations. 8.1 Power-Up/Down Characteristics In order ...
Page 30
Bus Operations This section provides an overview of device bus operations. The on-chip Write State Machine (WSM) manages all erase and program algorithms. The system CPU provides control of all in- system read, write, and ...
Page 31
Table 13. Chip Enable Truth Table CE2 NOTE: For single-chip applications, CE2 and CE1 can be connected to V 9.1.1 Bus Read Operation To ...
Page 32
Standby CE0, CE1, and CE2 can disable the device (see This manipulation of CEx substantially reduces device power consumption. D[15:0] outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, ...
Page 33
Table 14. Command Bus-Cycle Definitions (Sheet Scalable or Basic Command Command (2) Set Read Status Register SCS/BCS Clear Status Register SCS/BCS Write to Buffer SCS/BCS Word/Byte Program SCS/BCS Block Erase SCS/BCS Block Erase, Program SCS/BCS Suspend Block ...
Page 34
Read Operations The device supports four types of read modes: Read Array, Read Identifier, Read Status, and CFI query. Upon power-up or return from reset, the device defaults to read array mode. To change the ...
Page 35
Read Identifier Codes The Read identifier codes operation outputs the manufacturer code, device-code, and the block lock configuration codes for each block (See details on issuing the Read Device Identifier command). Page-mode reads are not supported in this read ...
Page 36
Table 16. Status Register Definitions WSMS ESS ECLBS bit 7 bit 6 bit 5 High Z When Status Register Bits Busy? SR7 = WRITE STATE MACHINE STATUS Ready 0 = Busy Yes SR6 ...
Page 37
Read Query/CFI The query register contains an assortment of flash product information such as block size, density, allowable command sets, electrical specifications and other product information. The data contained in this register conforms to the Common Flash Interface (CFI) ...
Page 38
Next, a word/byte count is given to the part with the Block Address. On the next write, a device start address is given along with the write buffer data. Subsequent writes provide additional device addresses and ...
Page 39
Program Resume To resume (i.e., continue) a program suspend operation, execute the Program Resume command. The Resume command can be written to any device address. When a program operation is nested within an erase suspend operation and the Program ...
Page 40
At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A program command sequence can also be issued during erase suspend to program data in ...
Page 41
Security Modes This device offers both hardware and software security features. Block lock operations, PRs, and VPEN allow the user to implement various levels of data protection. The following section describes security features in detail. 13.1 Set Block Lock-Bit ...
Page 42
If a clear block lock-bits operation is aborted due to V block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. ...
Page 43
Figure 16. Protection Register Memory Map NOTE not used in x16 mode when accessing the Protection Register map (See addressing). For x8 mode A0 is used (See Table 18. Word-Wide Protection Register Addressing Word Use LOCK Both 0 ...
Page 44
Table 19. Byte-Wide Protection Register Addressing (Sheet Factory 7 Factory 8 User 9 User A User B User C User D User E User F User NOTE: All address lines not specified ...
Page 45
To reconfigure the Status (STS) signal to other modes, the Configuration command is given followed by the desired configuration code. The three alternate configurations are all pulse mode for use as a system interrupt as described below. For these configurations, ...
Page 46
Appendix A Common Flash Interface The Common Flash Interface(CFI) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device independent, ...
Page 47
Table 21. Summary of Query Structure Output as a Function of Device and Mode Device Query start location in Type/ maximum device bus Mode width addresses x16 device x16 mode x16 device x8 mode NOTE: 1. The system must drive ...
Page 48
Table 23. Query Structure Offset 00h 01h (BA+2)h (2) Block Status Register 04-0Fh Reserved 10h CFI Query Identification String 1Bh System Interface Information 27h Device Geometry Definition Primary Intel-Specific Extended (3) P Query Table NOTES: 1. ...
Page 49
Table 25. CFI Identification (Sheet Offset Length 0000h means no second vendor-specified algorithm exists 19h 2 Secondary algorithm Extended Query Table address. 0000h means none exists A.5 System Interface Information The following device information can optimize system ...
Page 50
Table 27. Device Geometry Definition (Sheet Offset Length Number of erase block regions within device means no erase blocking; the device erases in “bulk” specifies the number ...
Page 51
Table 28. Primary Vendor-Specific Extended Query (Sheet (1) Offset Length P = 31h (P+5)h (P+6)h 4 (P+7)h (P+8)h (P+9)h 1 (P+A)h 2 (P+B)h (P+C)h 1 (P+D)h 1 NOTE: 1. Future devices may not support the described “Legacy ...
Page 52
Table 29. Protection Register Information (1) Offset Length P = 31h (P+E)h 1 (P+F)h (P+10)h 4 (P+11)h (P+12)h NOTE: 1. The variable pointer which is defined at CFI offset 15h. Table 30. Burst ...
Page 53
Appendix B Flow Charts Figure 17. Write to Buffer Flowchart Datasheet 28F256J3, 28F128J3, 28F640J3, 28F320J3 Start Setup - Write 0xE8 - Block Address Check Buffer Status - Perform read operation - Read Ready Status on signal SR7 No SR7 = ...
Page 54
Figure 18. Status Register Flowchart Start Command Cycle - Issue Status Register Command - Address = any dev ice address - Data = 0x70 Data Cycle - Read Status Register SR[7:0] SR7 = ' ...
Page 55
Figure 19. Byte/Word Program Flowchart Start Write 40H, Address Write Data and Address Read Status Register SR Full Status Check if Desired Byte/Word Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR ...
Page 56
Figure 20. Program Suspend/Resume Flowchart Start Write B0H Read Status Register SR SR Write FFH Read Data Array Done Reading Yes Write D0H Programming Resumed 56 Bus Operation Write Read Standby Standby ...
Page 57
Figure 21. Block Erase Flowchart Start Issue Single Block Erase Command 20H, Block Address Write Confirm D0H Block Address Read Status Register SR Full Status Check if Desired Erase Flash Block(s) Complete Datasheet 28F256J3, 28F128J3, 28F640J3, 28F320J3 Bus ...
Page 58
Figure 22. Block Erase Suspend/Resume Flowchart Start Write B0H Read Status Register SR.7 = SR.6 = Read Read or Program? Read Array Data Done? Write D0H Block Erase Resumed 58 Operation Standby Standby ...
Page 59
Figure 23. Set Block Lock-Bit Flowchart Start Write 60H, Block Address Write 01H, Block Address Read Status Register SR Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 ...
Page 60
Figure 24. Clear Lock-Bit Flowchart Start Write 60H Write D0H Read Status Register SR Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 ...
Page 61
Figure 25. Protection Register Programming Flowchart Start Write C0H (Protection Reg. Program Setup) Write Protect. Register Address/Data Read Status Register SR Yes Full Status Check if Desired Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See ...
Page 62
Appendix C Design Considerations C.1 Three-Line Output Control The device will often be used in large memory arrays. Intel provides five control inputs (CE0, CE1, CE2, OE#, and RP#) to accommodate multiple memory connections. This control ...
Page 63
C RP# Transitions CC PEN Block erase, program, and lock-bit configuration are not guaranteed if V the specified operating ranges, or RP# program, or lock-bit configuration, STS (in default mode) will remain low for a maximum ...
Page 64
Appendix D Additional Information Order Number 298130 298136 297833 290737 292280 292237 290606 297859 292222 292221 292218 292204 253418 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should ...
Page 65
Appendix E Ordering Information Package E = 56-Lead TSOP TE= 56-Lead TSOP RC = 64-Ball Easy BGA GE = 48-Ball VFBGA Product line designator ® for all Intel Flash products Device Density 256 = x8/x16 (256 Mbit) 128 = x8/x16 ...
Page 66
Datasheet ...