STM32F407IGH6 STMicroelectronics, STM32F407IGH6 Datasheet - Page 21

Microcontrollers (MCU) ARM M4 1024 FLASH 168 Mhz 192kB SRAM

STM32F407IGH6

Manufacturer Part Number
STM32F407IGH6
Description
Microcontrollers (MCU) ARM M4 1024 FLASH 168 Mhz 192kB SRAM
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F407IGH6

Core
ARM Cortex M4
Processor Series
STM32F4
Data Bus Width
32 bit
Maximum Clock Frequency
168 MHz
Program Memory Size
1024 KB
Data Ram Size
192 KB
On-chip Adc
Yes
Number Of Programmable I/os
140
Number Of Timers
10
Operating Supply Voltage
1.7 V to 3.6 V
Package / Case
UFBGA-176
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
24
Interface Type
CAN, I2C, I2S, SPI, UART
Program Memory Type
Flash
Lead Free Status / Rohs Status
 Details

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STM32F405xx, STM32F407xx
2.2.9
2.2.10
2.2.11
The DMA can be used with the main peripherals:
Flexible static memory controller (FSMC)
The FSMC is embedded in the STM32F405xx and STM32F407xx family. It has four Chip
Select outputs supporting the following modes: PCCard/Compact Flash, SRAM, PSRAM,
NOR Flash and NAND Flash.
Functionality overview:
LCD parallel interface
The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
Nested vectored interrupt controller (NVIC)
The STM32F405xx and STM32F407xx embed a nested vectored interrupt controller able to
manage 16 priority levels, and handle up to 87 maskable interrupt channels plus the 16
interrupt lines of the Cortex™-M4F.
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 23 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
SPI and I
I
USART
General-purpose, basic and advanced-control timers TIMx
DAC
SDIO
Camera interface (DCMI)
ADC.
Write FIFO
Maximum FSMC_CLK frequency for synchronous accesses is 60 MHz.
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support tail chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
2
C
2
S
Doc ID 022152 Rev 2
Description
21/167

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