W971GG8JB-25 Winbond Electronics, W971GG8JB-25 Datasheet
W971GG8JB-25
Specifications of W971GG8JB-25
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W971GG8JB-25 Summary of contents
Page 1
... Self Refresh Entry Command .......................................................................................... 21 7.3.8 Self Refresh Exit Command ............................................................................................. 22 7.3.9 Refresh Command ........................................................................................................... 22 7.3.10 No-Operation Command .................................................................................................. 23 7.3.11 Device Deselect Command .............................................................................................. 23 7.4 Read and Write access modes ........................................................................................................... 23 7.4.1 Posted CAS 7.4.1.1 Examples of posted .................................................................................................................... 23 operation ...................................................................... 23 CAS - 1 - W971GG8JB Publication Release Date: Aug. 11, 2010 Revision A01 ...
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... Differential Input/Output AC Logic Levels ........................................................................................... 65 9.14 AC Overshoot / Undershoot Specification ........................................................................................... 66 9.14.1 AC Overshoot / Undershoot Specification for Address and Control Pins: ........................ 66 9.14.2 AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask pins: .......... 66 10. TIMING WAVEFORMS ....................................................................................................................... 67 10.1 Command Input Timing ....................................................................................................................... 67 W971GG8JB Publication Release Date: Aug. 11, 2010 - 2 - Revision A01 ...
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... Active Power Down Mode Entry and Exit Timing ....................................................................... 83 10.31 Precharged Power Down Mode Entry and Exit Timing .............................................................. 83 10.32 Clock frequency change in precharge Power Down mode ........................................................ 84 11. PACKAGE SPECIFICATION .............................................................................................................. 85 Package Outline WBGA60 (8x12.5 mm 12. REVISION HISTORY .......................................................................................................................... ........................................................................................................ 85 Publication Release Date: Aug. 11, 2010 - 3 - W971GG8JB Revision A01 ...
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... GENERAL DESCRIPTION The W971GG8JB bits DDR2 SDRAM, organized as 16,777,216 words × 8 banks × 8 bits. This device achieves high speed transfer rates up to 1066Mb/sec/pin (DDR2-1066) for general applications. W971GG8JB is sorted into the following speed grades: -18, -25, 25I and -3. The -18 is compliant to the DDR2-1066 (6-6-6) specification. The -25/25I are compliant to the DDR2-800 (5-5-5) specification (the 25I industrial grade which is guaranteed to support -40° ...
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... Min. @ Max. Min. @ Max. Min. @ Max. Min. Min. Min. Min. Max. Max. Max. Max. Max. Max. ≤ Max. 85°C) Max W971GG8JB DDR2-1066 DDR2-800 DDR2-667 6-6-6 5-5-5 5-5-5 -18 -25/25I − 1.875 nS − 7.5 nS 1.875 nS 2 2.5 nS 2 3.75 nS 3. − ...
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... BA0 BA1 A10/AP A1 VSS VDD A12 VSSQ B DQS C VDDQ D DQ2 E VSSDL F RAS G CAS A11 L NC Publication Release Date: Aug. 11, 2010 - 6 - W971GG8JB 8 9 DQS VDDQ VSSQ DQ7 DQ0 VDDQ VSSQ DQ5 CLK VDD CLK ODT CS A0 VDD A4 A8 VSS A13 Revision A01 ...
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... DQ Power Supply: 1.8V ± 0.1V. DQ Power Supply DQ Ground DQ Ground. Isolated on the device for improved noise immunity. No Connection No connection. DLL Power Supply: 1.8V ± 0.1V. DLL Power Supply DLL Ground DLL Ground W971GG8JB DESCRIPTION are masked when CS is Publication Release Date: Aug. 11, 2010 Revision A01 registered ...
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... BLOCK DIAGRAM DECODER ROW DECODER DECODER ROW DECODER DECODER ROW DECODER DECODER ROW DECODER Publication Release Date: Aug. 11, 2010 - 8 - W971GG8JB ROW ROW ROW ROW Revision A01 ...
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... EMR(1). 13. The DDR2 SDRAM is now ready for normal operation. DDQ voltage ramp are driven from a single power converter output DDQ W971GG8JB *1 and ODT at a LOW state (all other ramps from 300 DD ≤ | 0.3 volts. DDQ during voltage ramp time to avoid DDQ ≥ ...
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... The mode register is divided into various fields depending on functionality. Burst length is defined by PRE MRS REF REF ALL MRD RP RFC MRD DLL min 200 Cycle Reset - 10 - W971GG8JB t IS ANY MRS EMRS EMRS CMD RFC MRD Follow OCD OIT Flow chart OCD OCD CAL ...
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... ODT setting. A10 DLL TM CAS Latency A7 Mode 0 Normal 1 Test Write recovery for Auto-precharge A11 A10 Reserved Figure 2 – Mode Register Set (MRS W971GG8JB Address Field BT Burst Length Mode Register Burst Length A3 Burst Type Sequential Interleave CAS Latency Latency Reserved Reserved Reserved ...
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... A10 A11 Strobe Function Matrix (DQS Enable) RDQS/DM 0 (Disable) 0 (Enable (Disable) 1 (Disable (Enable) 0 (Enable) RDQS 1 (Enable) 1 (Disable) RDQS Figure 3 – EMR ( W971GG8JB Address Field BT Rtt D.I.C DLL Extended Mode Register (1) A0 DLL Enable 0 Enable 1 Disable Driver strength control Output driver A1 Driver size ...
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... SELF A7 High Temperature Self Refresh Rate Enable 0 1 ≤ 95 °C the extended Self Refresh rate must be enabled by setting bit A7 to "1" CASE Figure 4 – EMR ( W971GG8JB ) must be satisfied to MRD Address Field 1 Extended Mode Register (2) 0* Disable 2 Enable* Publication Release Date: Aug. 11, 2010 ...
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... EMR (3) must be programmed during initialization for proper operation Note: 1. All bits in EMR(3) except BA0 and BA1 are reserved for future use and must be set to "0" when programming the EMR(3 Figure 5 – EMR (3) Publication Release Date: Aug. 11, 2010 - 14 - W971GG8JB Revision A01 ...
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... ALL OK EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit End Publication Release Date: Aug. 11, 2010 - 15 - W971GG8JB EMRS: Drive(0) DQ &DQS Low; DQS High Test Need Calibration EMRS: Enter Adjust Mode BL=4 code input to all DQs ...
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... NOP 1 Increase by 1 step 0 Decrease by 1 step 1 Increase by 1 step 0 Decrease by 1 step - 16 - W971GG8JB at bit time 1, and so forth. The driver Operation Pull-down driver strength NOP (No operation) NOP NOP Increase by 1 step Decrease by 1 step Increase by 1 step Increase by 1 step Decrease by 1 step ...
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... Figure 8. NOP NOP EMRS t OIT DQs high for Drive (1) DQs low for Drive (0) OCD calibration mode exit Figure 8 – OCD Drive Mode - 17 - W971GG8JB /t should be met fixed order and is not affected T3 NOP NOP NOP EMRS ...
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... Rval1 Rval2 Rval3 Input Pin Rval1 Rval2 Rval3 sw2 sw1 sw3 SSQ SSQ SSQ MOD window for proper operation. The timings are shown MOD Publication Release Date: Aug. 11, 2010 - 18 - W971GG8JB ,min and t ,max, and CKE MOD Revision A01 ...
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... Figure 11 – ODT update delay timing - t NOP NOP NOP t MOD,max Updating MOD window, until t MOD EMRS NOP NOP t MOD,max , as measured from outside MOD Publication Release Date: Aug. 11, 2010 - 19 - W971GG8JB NOP NOP t IS New setting ,max is met. MOD NOP NOP NOP AOND New setting Revision A01 ...
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... RP CK Figure 12 – Bank activate command cycle The minimum time interval between Bank Activate RC [nS FAW for a Precharge All command is equal the value for a single bank precharge RCD - 20 - W971GG8JB and t , respectively. The RAS RP (avg)[ns], and rounding (avg clocks, FAW where RP CK ...
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... Self Refresh entry is registered; however, the clock must be restarted and stable before the device can exit self refresh operation. min) and t (min) are satisfied. RAS( RTP Publication Release Date: Aug. 11, 2010 - 21 - W971GG8JB BA1, Revision A01 ...
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... CKE ≥ CMD Precharge NOP . XSRD t . REFI (max.) . REFI ≥ t RFC REF REF NOP Figure 13 – Refresh command - 22 - W971GG8JB for proper operation XSRD ). NOP or Deselect RFC ≥ t RFC NOP ANY Publication Release Date: Aug. 11, 2010 Revision A01 XSNR . XSNR ). RFC ...
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... Chapter 10) 7.4.1.1 Examples of posted Examples of a read followed by a write to the same bank where and where are shown in Figures 14 and 15, respectively. operation CAS - 23 - W971GG8JB * . The page , and is a minimum of 2 clocks for CCD RCDmin Publication Release Date: Aug. 11, 2010 Revision A01 ...
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... Burst read and write interrupt timing diagram in Chapter 10 Write A-Bank CL=3 RL=AL+CL=5 Dout0 Dout1 Dout2 Dout3 AL=0 Read A-Bank CL=3 RL=AL+CL=3 Dout0 Dout1 Dout2 Dout3 - 24 - W971GG8JB WL=RL-1=4 Din1 Din2 Din3 Din0 Write A-Bank WL=RL-1=2 Din0 Din1 Din2 Din3 Publication Release Date: Aug. 11, 2010 ...
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... The time from the completion of the burst write to bank precharge is the write recovery time (WR). (Example timing waveforms refer to 10.9 and 10.10 Data input (write) timing and Burst write operation diagram in Chapter 10) Sequential Addressing Interleave Addressing (decimal Publication Release Date: Aug. 11, 2010 - 25 - W971GG8JB (decimal Revision A01 ...
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... Minimum Write to Precharge timing BL clock after the un-interrupted burst end and not from the end of the actual burst end. (Example timing waveforms refer to 10.13 and 10.14 Burst read and write interrupt timing diagram in Chapter 10) W971GG8JB , where Publication Release Date: Aug. 11, 2010 ...
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... LOW HIGH HIGH LOW LOW HIGH HIGH Don’t Care , clocks” after a Read command. A new bank active RTP is satisfied. RAS - 27 - W971GG8JB BA0 Precharge Bank(s) LOW Bank 0 only HIGH Bank 1 only LOW Bank 2 only HIGH Bank 3 only LOW Bank 4 only HIGH ...
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... Auto-precharge RP ) from the previous bank activation has been satisfied. Limit) and (t Limit) diagram in Chapter 10 has been satisfied from the previous bank activation has been satisfied W971GG8JB (min) are satisfied. (Example timing ends (not at the RTP + (Example timing RTP RP CK ...
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... DD The DLL should locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down mode for proper read operation. W971GG8JB Minimum Delay between “From Command” to “To Command” BL/2 + max(RTP BL/2 + max(RTP ...
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... Clock frequency change in precharge Power Down mode diagram in Chapter 10) has been satisfied. Maximum power down duration is limited by CKE has been satisfied. A valid, executable CKE , t XP XARD - 30 - W971GG8JB if maximum posting of tREFI , after CKE goes HIGH. XARDS Publication Release Date: Aug. 11, 2010 Revision A01 ...
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... The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh requirements outlined in section 7.9. BA2 A13 BA1 A12 A10 A9-A0 BA0 A11 BA Row Address Column L Column BA Column H Column BA Column L Column BA Column H Column BA OP Code Publication Release Date: Aug. 11, 2010 - 31 - W971GG8JB NOTES CS RAS CAS 1 1 1,2 1,2 1,2 1 ...
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... Refer to the Command Truth Table (200 clocks) is satisfied. XSRD + )” in Self Refresh and Power Down. However ODT must be driven REF W971GG8JB 3 ACTION (N) NOTES Maintain Power Down 11, 12, 13 Power Down Exit 4, 8, 11, 12 Maintain Power Down 11, 13, 14 Self Refresh Exit Active Power Down 4, 8, 10, 11, Entry ...
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... BA, CA, A10 WRIT/WRITA H BA, RA ACT L BA, A10 PRE/PREA H X AREF/SELF L Op-Code MRS/EMRS - 33 - W971GG8JB ACTION NOTES NOP or Power down NOP or Power down ILLEGAL ILLEGAL Row activating Precharge/ Precharge all banks Auto Refresh or Self Refresh Mode/Extended register accessing NOP NOP Begin read Begin write ...
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... BA, CA, A10 READ/READA H L BA, CA, A10 WRIT/WRITA H BA, RA ACT BA, A10 PRE/PREA AREF/SELF L Op-Code MRS/EMRS - 34 - W971GG8JB ACTION NOTES Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP-> ...
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... READ/READA L BA, CA, A10 WRIT/WRITA H BA, RA ACT L BA, A10 PRE/PREA H X AREF/SELF L Op-Code MRS/EMRS - 35 - W971GG8JB ACTION NOTES NOP-> Bank active after t WR NOP-> Bank active after t WR ILLEGAL New write ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP-> Precharge after t WR NOP-> Precharge after t WR ...
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... WRITA Writing Reading with with Auto-precharge PRE, PREA PRE, PREA PRE, PREA Precharging - 36 - W971GG8JB CKEL Refreshing CKEL CKEL Autoomatic Sequence Command Sequence Read CKEL = CKE LOW, enter Power Down CKEH = CKE HIGH, exit Power Down CKEH = CKE HIGH, exit Self Refresh ...
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... V is expected to track variations in V REF ± (dc). REF is a system supply for signal termination resistors, is expected to be set equal parameters are measured with W971GG8JB RATING UNIT NOTES -1.0 ~ 2.3 V -0.5 ~ 2.3 V -0.5 ~ 2.3 V -0.5 ~ 2.3 V -55 ~ 100 ° ...
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... IL(ac) IHac Δ – 100 DDQ MIN 0.125 REF -0.3 -18 MIN. MAX 0.200 − V REF − 0.200 V REF - 38 - W971GG8JB NOM. MAX. UNIT NOTES 75 90 Ω 150 180 Ω Ω and I(V IH (ac) – I(V ) ILac) MAX 0.3 DDQ V - 0.125 REF -25/25I/-3 MIN ...
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... TT − -13.4 13 )/I must be less than 21 Ω for values of V DDQ OH /I must be less than 21 Ω for values max minus a noise margin are delivered to an SSTL_18 receiver W971GG8JB MIN. MAX. UNIT 1.0 2.0 pF − 0.25 pF 1.0 2.0 pF − 0.25 pF 2.5 3 ...
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... Data bus inputs are SWITCHING. -18 MAX RAS RASmin(IDD RAS RASmin(IDD) RCD 80 10 ≤ 85 ° C) CASE 50 45 Fast PDN Exit 25 MRS(12 Slow PDN Exit 10 MRS(12 RP(IDD) 55 Publication Release Date: Aug. 11, 2010 - 40 - W971GG8JB -25/25I -3 UNIT NOTES MAX. MAX. 1,2,3,4, 1,2,3,4, 1,2,3,4, 6,7 1,2,3,4, 1,2,3,4, 1,2,3,4, ...
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... REFI 10 10 ≤ 85 ° C) CASE = 0mA; OUT - RCD(IDD) CK(IDD RRD RRD(IDD) RCD 200 0.1V. /2 limits increase), when T DD CASE must be derated DD6 - 41 - W971GG8JB 1,2,3,4,5, 105 95 mA 1,2,3,4,5, 110 100 mA 1,2,3,4,5, 130 120 mA 1,2,3,4, 1,2,3,4, 1,2,3,4,5, 180 160 mA ≥ 85°C I must be derated ...
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... CK(IDD) t 11.25 RCD(IDD) t 11.25 RP(IDD) t 51.25 RC(IDD) t RASmin(IDD) t 70000 RASmax(IDD) t RRD(IDD)-1KB t FAW(IDD)-1KB t 127.5 RFC(IDD) DDR2-800 (-25/25I) 5-5 2.5 12.5 12.5 52 70000 7.5 7 127 W971GG8JB DDR2-667 (-3) UNIT 5-5-5 5 tCK 70000 nS 7.5 nS 37.5 nS 127.5 nS Publication Release Date: Aug. 11, 2010 Revision A01 ...
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... CK(avg CL=6 1.875 CK(avg CL=7 1.875 CK(avg) 0.48 0.48 -350 -325 7 7.5 7.5 125 200 325 325 0.6 -0.25 0.2 0.2 0.35 0. W971GG8JB DDR2-1066 (-18) 25 UNIT NOTES 6-6-6 MAX. − nS − nS − nS 70000 nS − nS − 7.8 μS − 3.9 μS − ...
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... Min. (t CH(abs) t CL(abs) − QHS RFC 200 AC,min t AC,min + 2 2.5 t AC,min t AC,min + CK(avg W971GG8JB DDR2-1066 (-18) 25 UNITS NOTES 6-6-6 MAX. − t CK(avg) 0.6 t CK(avg) 1.1 t 14,36 CK(avg) 0.6 t 14,37 CK(avg) 16,27,29, − pS 41,42,44 17,27,29, − pS 41,42,44 16,27,29, − pS 41,42,44 17,27,29, − ...
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... RP − 7.5 − 7.5 − 175 250 − − 375 − 375 − 0.6 -0.25 0.25 0.2 − − 0.2 − 0.35 0.35 − W971GG8JB DDR2-667 (-3) 25 UNITS NOTES 5-5-5 MIN. MAX. 15 − nS − − 70000 nS 127.5 − nS − 7.8 μS − ...
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... AC,min + 2 AC,min + AC,max 1 − − CK(avg) IS CK(avg) − Publication Release Date: Aug. 11, 2010 - 46 - W971GG8JB 25 UNITS NOTES MAX. − t CK(avg) 0 CK(avg) 1.1 t 14,36 CK(avg) 0.6 t 14,37 CK(avg) 16,27,29, − pS 41,42,44 17,27,29, − pS 41,42,44 16,27,29, − pS 41,42,44 17,27,29, − pS 41,42,44 − t CK(avg) ...
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... Logic levels V levels REF t IS(ref) – Figure 17 Differential input waveform timing – tIS and tIH VTT = VDDQ/2 25Ω IH(base) IS(base) IH(base IH(ref) IS(ref) IH(ref W971GG8JB V DDQ V min IH(ac) V min IH(dc) V REF(dc) V max IL(dc) V max IL(ac Publication Release Date: Aug. 11, 2010 Revision A01 ...
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... DQS slew rate is not equal to 2.0 V/nS, then the baseline values must be derated by adding the values from table of DDR2-667, DDR2-800 and DDR2-1066 tDS/tDH derating with differential data strobe (page 60). VTT + 2x mV VTT + x mV tLZ tRPRE begin point VTT - x mV VTT - tLZ,tRPRE begin point = Publication Release Date: Aug. 11, 2010 - 48 - W971GG8JB Revision A01 ...
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... WR [nCK] + tnRP [nCK {tRP [pS] / tCK(avg) [pS] }, where WR is the value programmed in the mode register set and RU stands for round up. Example: For DDR2-1066 6-6-6 at tCK(avg) = 1.875 nS with WR programmed to 8 nCK, tDAL = 8 + RU{11. 1.875 nS} [nCK [nCK [nCK DH(base) DS(base) DH(base DH(ref) DS(ref) DH(ref W971GG8JB V DDQ V min IH(ac) V min IH(dc) V REF(dc) V max IL(dc) V max IL(ac Publication Release Date: Aug ...
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... That is, these parameters should be met whether clock jitter is present or not. 29. These parameters are measured from a data signal (DM, DQ0, DQ1, etc.) transition edge to its respective data strobe signal (DQS, DQS , RDQS, RDQS ) crossing. W971GG8JB Publication Release Date: Aug. 11, 2010 - 50 - Revision A01 ...
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... N = 200 ⎡ ⎤ N ∑ × tCK(avg)) tCL ⎢ ⎥ j ⎣ ⎦ where N = 200 Publication Release Date: Aug. 11, 2010 - 51 - W971GG8JB DDR2-800 DDR2-1066 UNIT MIN. MAX. MIN. MAX. -100 100 - - -200 200 -180 180 pS -160 160 -160 160 ...
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... R(2per) ⎢ for tER R(3per) ⎢ ⎢ for tER R(4per) ⎢ for tER R(5per) ⎢ ⎢ ≤ ≤ for tER R(6 – 10per) ⎢ ≤ ≤ ⎢ for tER R(11 – ⎣ Publication Release Date: Aug. 11, 2010 - 52 - W971GG8JB 50per) Revision A01 ...
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... Publication Release Date: Aug. 11, 2010 - 53 - W971GG8JB MAX UNIT pS pS tJIT(duty),max pS tJIT(duty),max Revision A01 ...
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... Timings are specified with DQs and DM input slew rate of 1.0V/nS. 42. Timings are specified with CLK/ CLK differential slew rate of 2.0 V/nS. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/nS in differential strobe mode. W971GG8JB Publication Release Date: Aug. 11, 2010 - 54 - ...
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... W971GG8JB 1.0 V/nS Unit ΔtIS ΔtIH +210 +154 pS +203 +149 pS +193 +143 pS +180 +135 pS +160 +105 pS +127 +81 pS +60 +60 pS +55 ...
Page 56
... IL(dc) V max IL(ac Δ REF(dc) Setup Slew Rate = Falling Signal TF Δ Figure 20 – Illustration of nominal slew rate for nominal slew rate TR Δ Setup Slew Rate IL(ac)max = Rising Signal Publication Release Date: Aug. 11, 2010 - 56 - W971GG8JB REF region IH(ac)min REF(dc) TR Δ IS Revision A01 ...
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... Setup Slew Rate Falling Signal = Figure 21 – Illustration of tangent line for nominal line tangent tangent line TR Δ tangent line[V Setup Slew Rate Rising Signal = - V ] REF(dc) IL(ac)max TF Δ Publication Release Date: Aug. 11, 2010 - 57 - W971GG8JB t IH line REF region - V ] IH(ac)min REF(dc) TR Δ IS Revision A01 ...
Page 58
... IL(ac Hold Slew Rate REF(dc) Rising Signal = TR Δ Figure 22 – Illustration of nominal slew rate for nominal slew rate Δ Hold Slew Rate IL(dc)max Falling Signal = Publication Release Date: Aug. 11, 2010 - 58 - W971GG8JB t IH REF region TF Δ IH(dc)min REF(dc) TF Δ IH Revision A01 ...
Page 59
... Rising Signal Figure 23 – Illustration of tangent line for tangent tangent line nominal line TR Δ REF(dc) IL(ac)max TR Δ tangent line[V Hold Slew Rate Falling Signal = Publication Release Date: Aug. 11, 2010 - 59 - W971GG8JB t IH nominal line line REF region TF Δ IH(dc)min REF(dc) TF Δ IH Revision A01 ...
Page 60
... These values are typically not subject to production test. They are verified by design and characterization. the entire table) DQS/ DQS Differential Slew Rate 1.8 V/nS 1.6 V/nS 1 - -10 - - Publication Release Date: Aug. 11, 2010 - 60 - W971GG8JB 1.2 V/nS 1.0 V/nS 0 -47 14 -35 26 -23 38 -89 -12 - -52 -140 -40 -128 -28 -116 Revision A01 - - ...
Page 61
... REF(dc) IL(ac)max = Falling Signal TF Δ Figure 24 – Illustration of nominal slew rate for tDS (differential DQS, DQS ) nominal slew rate nominal slew rate TR Δ Setup Slew Rate Rising Signal Publication Release Date: Aug. 11, 2010 - 61 - W971GG8JB REF region IH(ac)min REF(dc Δ Revision A01 ...
Page 62
... Falling Signal = Figure 25 – Illustration of tangent line for tDS (differential DQS, DQS ) nominal line tangent line tangent line TR Δ Setup Slew Rate tangent line[V = Rising Signal - V ] REF(dc) IL(ac)max TF Δ Publication Release Date: Aug. 11, 2010 - 62 - W971GG8JB REF region - V ] IH(ac)min REF(dc) TR Δ Revision A01 ...
Page 63
... Rising Signal = TR Δ Figure 26 – Illustration of nominal slew rate for tDH (differential DQS, DQS ) nominal slew rate nominal slew rate TR Δ Hold Slew Rate IL(dc)max Falling Signal = Publication Release Date: Aug. 11, 2010 - 63 - W971GG8JB REF region TF Δ IH(dc)min REF(dc) TF Δ Revision A01 ...
Page 64
... Figure 27 – Illustration tangent line for tDH (differential DQS, DQS ) tangent tangent line nominal line TR Δ REF(dc) IL(ac)max tangent line [V Hold Slew Rate = Falling Signal Publication Release Date: Aug. 11, 2010 - 64 - W971GG8JB t DH nominal line line REF region TF Δ IH(dc)min REF(dc) TF Δ Revision A01 ...
Page 65
... DDQ V min IH(ac) V min IH(dc) V REF V V max TR IL(dc) V max IL(ac ΔTR V min - V IH(ac) REF Rising Slew = Δ W971GG8JB VALUE UNIT NOTES 0 DDQ 1.0 V 1.0 V/nS MAX. UNIT NOTES VDDQ + 0.6 V 0.5 x VDDQ + 0.175 V 0.5 x VDDQ + 0.125 V V DDQ Crossing point ...
Page 66
... Figure 29 – AC overshoot and undershoot definition −18 0.9 0.9 0.5 0.5 SS −18 0.9 0.9 0.19 0.19 SSQ Maximum Amplitude DDQ /V SS SSQ Maximum Amplitude Time (nS W971GG8JB −25/25I −3 UNIT 0.9 0.9 V 0.9 0.9 V 0.66 0.8 V-nS 0.66 0.8 V-nS −25/25I −3 UNIT 0.9 0.9 V 0.9 0 ...
Page 67
... TIMING WAVEFORMS 10.1 Command Input Timing CLK CLK CS RAS CAS WE A0~A13 BA0,1,2 10.2 Timing of the CLK Signals CLK CLK CLK CLK Refer to the Command Truth Table Publication Release Date: Aug. 11, 2010 - 67 - W971GG8JB IH(AC) V IL(AC Revision A01 ...
Page 68
... IH(ac) ODT t AOND Internal Term Res. 10.4 ODT Timing for Power Down Mode T0 T1 CLK CLK CKE IH(ac) ODT Internal Term Res. t AONPD(min) t AONPD(max IL(ac) t AOFD AON(min) t AOF(min) t AON(max IL(ac) t AOFPD(max) t AOFPD(min W971GG8JB AOF(max Publication Release Date: Aug. 11, 2010 Revision A01 ...
Page 69
... ODT Timing mode switch at entering power down mode W971GG8JB Publication Release Date: Aug. 11, 2010 - 69 - Revision A01 ...
Page 70
... T7 t AXPD t IS ODT V IL(ac) Internal Term Res ODT V IL(ac) Internal R TT Term Res IH(ac) ODT Internal Term Res IH(ac) ODT Internal Term Res. t AONPD(max) Publication Release Date: Aug. 11, 2010 - 70 - W971GG8JB T8 T9 T10 AOFD t AOFPD(max) R RTT TT t AOND R TT Revision A01 ...
Page 71
... T1 T2 CLK/CLK Posted CAS CMD NOP NOP READ A DQS, DQS DQ DQSmax NOP NOP NOP NOP NOP NOP NOP NOP W971GG8JB t RPST DQSmax NOP NOP NOP NOP NOP NOP ≤ t DQSCK Dout Dout Dout Dout Publication Release Date: Aug. 11, 2010 Revision A01 ...
Page 72
... Data input (write) timing DQS DQS DQS DQS t WPRE DQ DM 10.10 Burst write operation: RL=5 (AL=2, CL=3, WL=4, BL= DQSH DQSL V (ac) V (dc (dc (ac (ac) IH DMin DMin DMin V (ac W971GG8JB t WPST (dc) IH DMin V (dc) IL Publication Release Date: Aug. 11, 2010 Revision A01 ...
Page 73
... The seamless burst write operation is supported by enabling a write command every other clock for operation, every four clocks for operation. This operation is allowed regardless of same or different banks as long as the banks are activated NOP NOP NOP DIN DIN DIN DIN Publication Release Date: Aug. 11, 2010 - 73 - W971GG8JB NOP NOP NOP DIN DIN DIN DIN Revision A01 ...
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... T4 T5 NOP NOP NOP READ B Dout Dout Dout Dout Dout NOP Write B NOP NOP Din Din Din Din Din W971GG8JB NOP NOP NOP Dout Dout Dout Dout Dout Dout Dout NOP NOP NOP Din Din Din Din Din Din Din B1 B2 ...
Page 75
... Write operation with Data Mask: WL=3, AL=0, BL=4) Data Mask Timing DQS/ DQS DQ DM CLK CLK CMDMAND Write Case 1: min t DQSS DQS/DQS DQ DM Case 2: max t DQSS DQS/DQS IH(ac) V IH(ac) IH(dc) IH(dc IL(dc) IL(dc IL(ac) IL(ac DQSS (min DQSS (max W971GG8JB t WR Publication Release Date: Aug. 11, 2010 Revision A01 ...
Page 76
... DQS, DQS DQ's first 4-bit prefetch second 4-bit prefetch NOP Precharge NOP Dout Dout NOP NOP NOP AL + BL/2 clks Dout Dout A0 A1 ≥ t RTP - 76 - W971GG8JB Bank A NOP NOP Activate ≥ Dout Dout Precharge NOP NOP Dout Dout Dout Dout Dout Dout Publication Release Date: Aug ...
Page 77
... NOP READA AL + BL/2 clks DQS, DQS DQ Precharge NOP NOP ≥ t RAS ≥ t RTP NOP NOP Precharge ≥ t RAS ≥ t RTP - 77 - W971GG8JB Bank A NOP NOP NOP Activate ≥ Dout Dout Dout Dout Bank A NOP NOP NOP Activate ≥ Dout Dout Dout Dout ...
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... Burst write operation followed by precharge (RL- CLK/CLK Post CAS NOP CMD WRITE A DQS, DQS DQ NOP NOP NOP DIN DIN DIN DIN W971GG8JB NOP NOP NOP Precharge Completion of the Burst Write ≥ Publication Release Date: Aug. 11, 2010 Revision A01 RTP ...
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... T5 NOP NOP NOP NOP DIN A0 DIN A1 DIN A2 DIN NOP NOP NOP NOP Dout Dout A0 A1 ≥ t RTP t RTP Precharge begins here - 79 - W971GG8JB NOP NOP Precharge A Completion of the Burst Write ≥ RTP Bank A NOP NOP Activate ≥ Dout Dout Dout Dout Dout ...
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... NOP NOP NOP + t RTP Dout Dout RTP Precharge begins here =3, BL=4, t RCD NOP NOP NOP Auto-precharge begins (AL + BL/ min W971GG8JB RTP Bank A NOP NOP Activate Dout Dout ≤ 2clks) RTP Bank A NOP NOP NOP Activate ≥ Dout Dout Dout Dout A0 A1 ...
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... NOP NOP NOP Auto-precharge begins ≥ Limit): WL=2, WR=2, BL= NOP NOP NOP Completion of the Burst Write DIN DIN DIN DIN W971GG8JB 2clks) RTP ≤ Bank A NOP NOP Activate t RP min. Dout Dout Dout Dout Bank A NOP NOP NOP Activate Auto-precharge Begins ≥ ...
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... Self Refresh Timing CLK CLK CKE ODT V IL(ac CMD Limit): WL=4, WR=2, BL= IL(ac AOFD Self IH(ac) IH(dc) Refresh V V IL(dc) IL(ac W971GG8JB RP Tm ≥ t XSNR ≥ t XSRD V IH(ac tIS NOP Non-Read NOP Command Command Publication Release Date: Aug. 11, 2010 Revision A01 = Read ...
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... T1 CLK CLK Precharge NOP CMD CKE Precharge Power Down Entry T2 NOP Active Power Down Exit NOP NOP Precharge Power Down - 83 - W971GG8JB Tn Tn+1 Tn+2 Valid NOP NOP Command t or XARD XARDS Tn+1 Tn+2 Valid NOP NOP NOP Command Exit Publication Release Date: Aug. 11, 2010 ...
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... X+1 Y Y+1 Y+2 NOP t Frequency change IS Occurs here Stable new clock before power down exit Publication Release Date: Aug. 11, 2010 - 84 - W971GG8JB Y+3 Y+4 z DLL NOP NOP Valid RESET 200 Clocks ODT is off during DLL RESET Revision A01 ...
Page 85
... Pin A1 index ccc C SEATING PLANE MAX. --- 1.20 0.40 --- 0.45 0.50 12.60 8.10 8.00 Note: 1. Ball land : 0.5mm --- 0.15 --- 0.20 --- 0. W971GG8JB E B Ball Land Ball Opening 2. Ball opening : 0.4mm 3. PCB Ball land suggested 0.4mm Publication Release Date: Aug. 11, 2010 Revision A01 aaa A ...
Page 86
... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. PAGE DESCRIPTION All Initial formally data sheet Important Notice Publication Release Date: Aug. 11, 2010 - 86 - W971GG8JB Revision A01 ...