KM416S8030BT-F8 Samsung Semiconductor, KM416S8030BT-F8 Datasheet
KM416S8030BT-F8
Specifications of KM416S8030BT-F8
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KM416S8030BT-F8 Summary of contents
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... KM416S8030B 128Mbit SDRAM * Samsung Electronics reserves the right to change products or specification without notice 16Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.1 June 1999 CMOS SDRAM Rev. 0.1 Jun. 1999 ...
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... Notes : 5. For -8/H/L, tRDL=1CLK and tDAL=1CLK+20ns is also supported . SAMSUNG recommands tRDL=2CLK and tDAL=2CLK + 20ns. • Added -10 bining product Before = 15ns CC V (min 15ns IH CC CMOS SDRAM After Input leakage current Output open @ DC characteristic table After CKE V (max 10ns IL CC CKE V (min), CS ...
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... ORDERING INFORMATION KM416S8030BT-G/FA KM416S8030BT-G/F8 KM416S8030BT-G/FH KM416S8030BT-G/FL KM416S8030BT-G/F10 66MHz(CL=2 &3) Data Input Register Column Decoder Latency & Burst Length Programming Register ...
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... Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device. CMOS SDRAM 54Pin TSOP (II) (400mil x 875mil) (0.8 mm Pin pitch) ...
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... -10 LI 3ns. 3ns 1MHz, V =1.4V 200 mV) A REF Symbol Min C 2.5 CLK C 2 2.5 ADD C 4.0 OUT CMOS SDRAM Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50 Max Unit Max Unit 4.0 pF 5.0 pF 5.0 pF 6.5 pF Rev. 0.1 Jun. 1999 ...
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... IH N Input signals are changed one time during 20ns CKE V (min), CLK V (max Input signals are stable Page burst 4Banks Activated t = 2CLKs CCD t t (min CKE 0. CMOS SDRAM Version - 150 150 140 10ns 10ns 180 170 145 220 220 210 G 1.5 ...
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... RRD t (min) 20 RCD t (min (min) 45 RAS t (max) RAS t (min (min) RDL t (min) DAL t (min) CDL t (min) BDL t (min) CCD CAS latency=3 CAS latency=2 CMOS SDRAM = Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2 Output (Fig output load circuit Version - - 100 ...
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... Measure in linear 1.37 region : 1.2V ~ 1.8V Measure in linear 1.30 region : 1.2V ~ 1.8V Measure in linear 2.8 region : 1.2V ~ 1.8V Measure in linear 2.0 region : 1. use these values to design to use these values to design to CMOS SDRAM - Min Max Min Max Min Max 1000 1000 1000 ...
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... Min I (mA) 200 0.0 17.7 26.9 150 33.3 37.6 46.6 100 48.0 49.5 50.7 50 51.5 54.2 54 0.5 CMOS SDRAM 66MHz and 100MHz Pull-up 1 1.5 2 2.5 3 Voltage I Min (100MHz Min (66MHz Max (66 and 100MHz) OH 66MHz and 100MHz Pull-down 1 1.5 2 2.5 3 ...
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... Minimum V clamp current DD (Referenced Voltage I (mA) Minimum V clamp current -10 -20 -30 -40 -50 -60 Voltage I (mA) Rev. 0.1 Jun. 1999 CMOS SDRAM ) 3 0 ...
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... MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. ...