MPC5200CVR400B Freescale Semiconductor, MPC5200CVR400B Datasheet - Page 34

• Manufacturer Part Number: MPC5200CVR400B
• Description: IC MPU 32BIT 400MHZ 272-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC5200CVR400B

• Processor Type: MPC52xx PowerPC 32-Bit
• Speed: 400MHz
• Voltage: 1.5V
• Mounting Type: Surface Mount
• Package / Case: 272-PBGA
• Processor Series: MPC52xx
• Core: e300
• Development Tools By Supplier: MEDIA5200KIT1E
• Maximum Clock Frequency: 400 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 2.5 V, 3.3 V
• Minimum Operating Temperature: - 40 C
• Core Size: 32 Bit
• No. Of I/o's: 56
• Ram Memory Size: 16KB
• Cpu Speed: 400MHz
• No. Of Timers: 8
• Embedded Interface Type: CAN, I2C, SCI, SPI
• No. Of Pwm Channels: 8
• Digital Ic Case Style: TEPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Electrical and Thermal Characteristics
The MPC5200 ATA Host Controller design makes data available coincidentally with the active edge of the
WRITE strobe in PIO and Multiword DMA modes.
All ATA transfers are programmed in terms of system clock cycles (IP bus clocks) in the ATA Host
Controller timing registers. This puts constraints on the ATA protocols and their respective timing modes
in which the ATA Controller can communicate with the drive.
Faster ATA modes (i.e., UDMA 0, 1, 2) are supported when the system is running at a sufficient frequency
to provide adequate data transfer rates. Adequate data transfer rates are a function of the following:
The ATA clock is the same frequency as the IP bus clock in MPC5200. See the MPC5200 User Manual [1].
34
•
•
•
•
•
t2i
tA
tB
t0
t1
t2
t3
t4
t5
t6
t9
Write data is latched by the drive at the inactive edge of the WRITE strobe. This gives ample
setup-time beyond that required by the ATA-4 specification.
Data is held unchanged until the next active edge of the WRITE strobe. This gives ample
hold-time beyond that required by the ATA-4 specification.
The MPC5200 operating frequency (IP bus clock frequency)
Internal MPC5200 bus latencies
Other system load dependent variables
Cycle Time
Address valid to DIOR/DIOW setup
DIOR/DIOW pulse width 16-bit
DIOR/DIOW recovery time
DIOW data setup
DIOW data hold
DIOR data setup
DIOR data hold
DIOR/DIOW to address
valid hold
IORDY setup
IORDY pulse width
8-bit
PIO Timing Parameter
All output timing numbers are specified for nominal 50 pF loads.
Table 27. PIO Mode Timing Specifications
MPC5200 Data Sheet, Rev. 4
Min/Max
(ns)
max
max
min
min
min
min
min
min
min
min
min
min
NOTE
Mode 0
1250
(ns)
600
165
290
70
60
30
50
20
35
—
5
Mode 1
1250
(ns)
383
125
290
50
45
20
35
15
35
—
5
Mode 2
1250
(ns)
240
100
290
30
30
15
20
10
35
—
5
Mode 3
1250
(ns)
180
30
80
80
70
30
10
20
10
35
5
Freescale Semiconductor
Mode 4
1250
(ns)
120
25
70
70
25
20
10
20
10
35
5
SpecID
A8.10
A8.11
A8.1
A8.2
A8.3
A8.4
A8.5
A8.6
A8.7
A8.8
A8.9