MPC5200CVR400B Freescale Semiconductor, MPC5200CVR400B Datasheet - Page 13

• Manufacturer Part Number: MPC5200CVR400B
• Description: IC MPU 32BIT 400MHZ 272-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC5200CVR400B

• Processor Type: MPC52xx PowerPC 32-Bit
• Speed: 400MHz
• Voltage: 1.5V
• Mounting Type: Surface Mount
• Package / Case: 272-PBGA
• Processor Series: MPC52xx
• Core: e300
• Development Tools By Supplier: MEDIA5200KIT1E
• Maximum Clock Frequency: 400 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 2.5 V, 3.3 V
• Minimum Operating Temperature: - 40 C
• Core Size: 32 Bit
• No. Of I/o's: 56
• Ram Memory Size: 16KB
• Cpu Speed: 400MHz
• No. Of Timers: 8
• Embedded Interface Type: CAN, I2C, SCI, SPI
• No. Of Pwm Channels: 8
• Digital Ic Case Style: TEPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

There is a separate oscillator for the independent Real-Time Clock (RTC) system.
The MPC5200 clock generation uses two phase locked loop (PLL) blocks.
3.2.1
3.2.2
3.2.3
Freescale Semiconductor
•
•
NOTES:
1
2
3
SYS_XTAL frequency
Oscillator start-up time
RTC_XTAL frequency
SYS_XTAL frequency
SYS_XTAL cycle time
SYS_XTAL clock input jitter
System VCO frequency
System PLL relock time
The SYS_XTAL frequency and PLL Configuration bits must be chosen such that the resulting system frequency,
CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies.
This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different
types of jitter can exist on the input to core_sysclk, systemic and true random jitter. True random jitter is rejected, but
the PLL. Systemic jitter will be passed into and through the PLL to the internal clock circuitry, directly reducing the
operating frequency.
Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required
for the PLL lock after a stable Vdd and core_sysclk are reached during the power-on reset sequence. This
specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.
The system PLL (SYS_PLL) takes an external reference frequency and generates the internal
system clock. The system clock frequency is determined by the external reference frequency and
the settings of the SYS_PLL configuration.
The G2_LE core PLL (CORE_PLL) generates a master clock for all of the CPU circuitry. The
G2_LE core clock frequency is determined by the system clock frequency and the settings of the
CORE_PLL configuration.
System Oscillator Electrical Characteristics
RTC Oscillator Electrical Characteristics
System PLL Electrical Characteristics
Characteristic
Characteristic
Characteristic
Table 8. System Oscillator Electrical Characteristics
Table 9. RTC Oscillator Electrical Characteristics
Table 10. System PLL Specifications
Symbol
Symbol
Symbol
T
f
f
f
t
f
sys_xtal
sys_xtal
VCOsys
up_osc
rtc_xtal
sys_xtal
t
t
jitter
lock
MPC5200 Data Sheet, Rev. 4
Notes
Notes
Notes
(1)
(1)
1
2
3
15.6
15.6
66.6
Min
Min
Min
250
—
—
—
—
Typical
Typical
Typical
32.768
33.3
33.3
30.0
533
—
—
—
Electrical and Thermal Characteristics
Max
35.0
Max
Max
35.0
28.5
100
150
800
100
—
MHz
MHz
MHz
Unit
Unit
Unit
kHz
µs
ns
ps
µs
SpecID
SpecID
SpecID
O1.1
O1.2
O2.1
O3.1
O3.2
O3.3
O3.4
O3.5
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