XC4VFX140-10FFG1517I Xilinx Inc, XC4VFX140-10FFG1517I Datasheet - Page 341
XC4VFX140-10FFG1517I
Manufacturer Part Number
XC4VFX140-10FFG1517I
Description
IC FPGA VIRTEX-4FX 140K 1517FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX140-10FFG1517I
Number Of Logic Elements/cells
142128
Number Of Labs/clbs
15792
Total Ram Bits
10174464
Number Of I /o
768
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
IDELAYCTRL Overview
R
IDELAYCTRL Primitive
IDELAYCTRL Ports
If the IDELAY or ISERDES primitive is instantiated with the IOBDELAY_TYPE attribute
set to FIXED or VARIABLE, the IDELAYCTRL module must be instantiated. The
IDELAYCTRL module continuously calibrates the individual delay elements (IDELAY) in
its region (see
temperature variations. The IDELAYCTRL module calibrates IDELAY using the user
supplied REFCLK.
Figure 7-13
RST - Reset
The reset input pin (RST) is an active-High asynchronous reset. IDELAYCTRL must be
reset after configuration (and the REFCLK signal has stabilized) to ensure proper IDELAY
operation. A reset pulse width T
after configuration.
IDELAY U1
//Set IOBDELAY_TYPE attribute to VARIABLE for Variable Delay Mode
//synthesis attribute IOBDELAY_TYPE of U1 is "VARIABLE";
//synthesis attribute IOBDELAY_VALUE of U1 is 0;
(
);
O(data_output)
I(data_input),
C(clkdiv),
CE(dlyce),
INC(dlyinc),
RST(dlyrst)
shows the IDELAYCTRL primitive.
Figure 7-15, page
Figure 7-13: IDELAYCTRL Primitive
www.xilinx.com
343), to reduce the effects of process, voltage, and
IDELAYCTRL_RPW
REFCLK
RST
IDELAYCTRL
ug070_7_13_080104
RDY
is required. IDELAYCTRL must be reset
ILOGIC Resources
341
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