XC4VFX140-10FFG1517I Xilinx Inc, XC4VFX140-10FFG1517I Datasheet - Page 173
XC4VFX140-10FFG1517I
Manufacturer Part Number
XC4VFX140-10FFG1517I
Description
IC FPGA VIRTEX-4FX 140K 1517FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX140-10FFG1517I
Number Of Logic Elements/cells
142128
Number Of Labs/clbs
15792
Total Ram Bits
10174464
Number Of I /o
768
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Resource Utilization
Performance
Design Files
The resources used in implementing the solution described above with a 400 MHz
FASTCLK are as follows.
The design was implemented using the ISE 8.1i software with default settings for MAP,
Place, and Route. The approximate resource count was 20 LUTs and 24 flip-flops per FIFO.
One DCM is required to generate a 400 MHz clock if a 200 MHz input clock is available.
Two DCMs are needed if only a 100 MHz input clock is available. One extra BUFG was
used per device.
The maximum FASTCLK frequency for each speed grade is Global Clock Tree FMAX, as
given in the
RDCLK and WRCLK frequency is 1/3 the FASTCLK frequency. If the system design
guarantees that there is at least one clock cycle between all reads and all writes, then the
maximum RDCLK and WRCLK frequency is 2/3 the FASTCLK frequency. If the system
design guarantees that there are at least two clock cycles between all reads and all writes,
then the RDCLK and WRCLK frequency can be equal to the FASTCLK frequency.
All the necessary files required for the above design are contained in a ZIP archive
downloadable from the Xilinx website at:
Open the ZIP archive and extract FIFO16_solution2.zip.
https://secure.xilinx.com/webreg/clickthrough.do?cid=30163
Virtex-4 Data
Sheet. If any back-to-back reads or writes occur, the maximum
www.xilinx.com
FIFO16 Error Condition and Work-Arounds
173
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