AD7791BRMZ Analog Devices Inc, AD7791BRMZ Datasheet - Page 12

• Manufacturer Part Number: AD7791BRMZ
• Description: IC ADC 24BIT BUFFERED LP 10MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7791BRMZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 24
• Sampling Rate (per Second): 120
• Number Of Converters: 1
• Power Dissipation (max): 230µW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP (0.118", 3.00mm Width)
• Resolution (bits): 24bit
• Sampling Rate: 120SPS
• Input Channel Type: Differential
• Supply Current: 145µA
• Digital Ic Case Style: SOP
• No. Of Pins: 10
• Number Of Elements: 1
• Resolution: 24Bit
• Architecture: Delta-Sigma
• Sample Rate: 0.12KSPS
• Input Polarity: Bipolar
• Input Type: Voltage
• Rated Input Volt: ±2.5V
• Differential Input: Yes
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 2.5V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 225uW
• Integral Nonlinearity Error: ±15ppm of FSR
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 10
• Package Type: MSOP
• Input Signal Type: Differential
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD7791
Bit Location
MR3
MR2
MR1
MR0
Table 10. Operating Modes
MD1
0
0
1
1
FILTER REGISTER (RS1, RS0 = 1, 0; POWER-ON/RESET = 0x04)
The filter register is an 8-bit register from which data can be read or to which data can be written. This register is used to set the output word
rate. Table 11 outlines the bit designations for the filter register. FR0 through FR7 indicate the bit locations, FR denoting the bits are in the
filter register. FR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
FR7
0(0)
Table 11. Filter Register Bit Designations
Bit Location
FR7–FR6
FR5–FR4
FR3
FR2–FR0
MD0
0
1
0
1
FR6
0(0)
Bit Name
0
CLKDIV1–
CDIV0
0
FS2–FS0
Bit Name
BO
U/B
BUF
0
Mode
Continuous Conversion Mode
(Default)
Reserved
Single Conversion Mode
Power-Down Mode
These bits must be programmed with a Logic 0 for correct operation.
This bit must be programmed with a Logic 0 for correct operation.
Description
Burnout Current Enable Bit. When this bit is set to 1 by the user, the 100 nA current sources in the signal
path are enabled. When BO = 0, the burnout currents are disabled. The burnout currents can be enabled
only when the buffer is active.
Unipolar/Bipolar Bit. Set by user to enable unipolar coding, i.e., zero differential input will result in
0x000000 output and a full-scale differential input will result in 0xFFFFFF output. Cleared by the user to
enable bipolar coding. Negative full-scale differential input will result in an output code of 0x000000,
zero differential input will result in an output code of 0x800000, and a positive full-scale differential
input will result in an output code of 0xFFFFFF.
Configures the ADC for buffered or unbuffered mode of operation. If cleared, the ADC operates in
unbuffered mode, lowering the power consumption of the device. If set, the ADC operates in buffered
mode, allowing the user to place source impedances on the front end without contributing gain errors
to the system.
This bit must be programmed with a Logic 0 for correct operation.
Description
These bits are used to operate the AD7791 in the lower power modes. The clock is internally divided and
the power is reduced. In the low power modes, the update rates will scale with the clock frequency so
that dividing the clock by 2 causes the update rate to be reduced by a factor of 2 also.
00
01
10
11
These bits set the output word rate of the ADC. The update rate influences the 50 Hz/60 Hz rejection and
the noise. See Table 12, which shows the allowable update rates when normal power mode is used. In
the low power modes, the update rate is scaled with the clock frequency. For example, if the internal
clock is divided by a factor of 2, the corresponding update rates will be divided by 2 also.
FR5
CDIV1(0)
Normal Mode
Clock Divided by 2
Clock Divided by 4
Clock Divided by 8
FR4
CDIV0(0)
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FR3
0(0)
FR2
FS2(1)
FR1
FS1(0)
FR0
FS0(0)