UPD78F9502MA-CAC-A NEC, UPD78F9502MA-CAC-A Datasheet
UPD78F9502MA-CAC-A
Specifications of UPD78F9502MA-CAC-A
Related parts for UPD78F9502MA-CAC-A
UPD78F9502MA-CAC-A Summary of contents
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Preliminary User’s Manual PD78F9500, 78F9501, 78F9502 8-Bit Single-Chip Microcontrollers PD78F9500 PD78F9501 PD78F9502 Document No. U18681EJ1V0UD00 (1st edition) Date Published June 2007 NS © 2007 Printed in Japan ...
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Preliminary User’s Manual U18681EJ1V0UD ...
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... IH 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction input pin is unconnected possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry ...
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... NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others ...
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Target Readers This manual is intended for user engineers who wish to understand the functions of the PD78F9500, 78F9501, 78F9502 in order to design and develop its application systems and programs. Purpose This manual is intended to give users on ...
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Conventions Data significance: Active low representation: Note: Caution: Remark: Numerical representation: Binary ... Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices PD78F9500, 78F9501, ...
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... NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing ...
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... RESET ..............................................................................................................................................21 2.2.5 V ....................................................................................................................................................21 DD 2.2.6 V ....................................................................................................................................................21 SS 2.3 Pin I/O Circuits and Connection of Unused Pins ......................................................................22 CHAPTER 3 CPU ARCHITECTURE ......................................................................................................23 3.1 Memory Space ..............................................................................................................................23 3.1.1 Internal program memory space........................................................................................................26 3.1.2 Internal data memory space ..............................................................................................................27 3.1.3 Special function register (SFR) area..................................................................................................27 3.1.4 Data memory addressing ..................................................................................................................27 3.2 Processor Registers.....................................................................................................................30 3 ...
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Stack addressing............................................................................................................................... 47 CHAPTER 4 PORT FUNCTIONS........................................................................................................... 48 4.1 Functions of Ports........................................................................................................................ 48 4.2 Port Configuration........................................................................................................................ 49 4.2.1 Port 2 ................................................................................................................................................ 49 4.2.2 Port 3 ................................................................................................................................................ 53 4.2.3 Port 4 ................................................................................................................................................ 54 4.3 Registers Controlling Port Functions ........................................................................................ 55 ...
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Watchdog timer operation in STOP mode (when “low-speed internal oscillator can be stopped by software” is selected by option byte) ................................................................................................96 7.4.4 Watchdog timer operation in HALT mode (when “low-speed internal oscillator can be stopped by software” is selected ...
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CHAPTER 14 FLASH MEMORY..........................................................................................................136 14.1 Features.....................................................................................................................................136 14.2 Memory Configuration .............................................................................................................137 14.3 Functional Outline ....................................................................................................................137 14.4 Writing with Flash Memory Programmer ...............................................................................138 14.5 Programming Environment .....................................................................................................139 14.6 Processing of Pins on Board ..................................................................................................140 14.6.1 EXCLK pin..................................................................................................................................... 140 14.6.2 RESET pin .................................................................................................................................... ...
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APPENDIX A DEVELOPMENT TOOLS...............................................................................................212 A.1 Software Package ......................................................................................................................215 A.2 Language Processing Software ...............................................................................................215 A.3 Control Software ........................................................................................................................216 A.4 Flash Memory Writing Tools .....................................................................................................216 A.5 Debugging Tools (Hardware)....................................................................................................217 A.5.1 When using in-circuit emulator QB-78K0SKX1 ...............................................................................217 A.5.2 When using in-circuit emulator QB-MINI2 ...
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Features O 78K0S CPU core O ROM and RAM capacities Item Part number PD78F9500 1 KB PD78F9501 2 KB PD78F9502 Minimum instruction execution time: 0.2 s (with 10 MHz@4.0 to 5.5 V operation) O Clock High-speed ...
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Ordering Information Part Number PD78F9 - - - [Part number list] PD78F9500MA-CAC-A PD78F9501MA-CAC-A PD78F9502MA-CAC-A 14 CHAPTER 1 OVERVIEW Semiconductor component Blank Conventional -A Lead-free Quality Grades Standard (General management) Blank Package type MA-CAC Plastic SSOP Number of ...
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Pin Configuration (Top View) 10-pin plastic SSOP P20/TOH1 P40 V V P23/EXCLK INTP0, INTP1: External interrupt input P20 to P23: Port 2 P30, P34: Port 3 P40, P43: Port 4 RESET: Reset CHAPTER 1 OVERVIEW ...
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Product Lineup The following table shows the product lineup of the 78K0S/Kx1+. Part Number 78K0S/KU1+ Item Number of pins 10 pins Internal Flash memory memory RAM Supply voltage Minimum instruction execution time System clock (oscillation frequency) Clock for ...
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Block Diagram TOH1/P20 8-bit TIMER H1 LOW-SPEED INTERNAL OSCILLATOR WATCHDOG TIMER INTP0/P21 INTERRUPT CONTROL INTP1/P32 CHAPTER 1 OVERVIEW 78K0S FLASH CPU MEMORY CORE INTERNAL HIGH-SPEED RAM Preliminary User’s Manual U18681EJ1V0UD PORT 2 4 P20-P23 P32 ...
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Functional Outline Item Internal Flash memory memory High-speed RAM Memory space High-speed system clock Internal high-speed oscillation clock Internal low-speed oscillation clock General-purpose registers Instruction execution time I/O port Timer Timer output Vectored interrupt External sources Internal Reset Supply ...
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... Pin Function List (1) Port pins Pin Name I/O P20 I/O Port 2. 4-bit I/O port. P21 Can be set to input or output mode in 1-bit units. P22 An on-chip pull-up resistor can be connected by setting Note software. P23 P32 I/O Port 3 An on-chip pull-up resistor can be connected by setting software. ...
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... These pins can be set to the following operation modes in 1-bit units. (1) Port mode P20 to P23 function as a 4-bit I/O port. Each bit of this port can be set to the input or output mode by using port mode register 2 (PM2). In addition, an on-chip pull-up resistor can be connected to the port by using pull- up resistor option register 2 (PU2). (2) Control mode P20 to P23 function to output a timer signal, and input an external interrupt request signal ...
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... P40 and P43 (Port 4) P40 and P43 constitute a 2-bit I/O port. Each bit of this port can be set to the input or output mode by using port mode register 4 (PM4). In addition, an on-chip pull-up resistor can be connected to the port by using pull-up resistor option register 4 (PU4). ...
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... Pin I/O Circuits and Connection of Unused Pins Table 2-1 shows I/O circuit type of each pin and the connections of unused pins. For the configuration of the I/O circuit of each type, refer to Figure 2-1. Table 2-1. Types of Pin I/O Circuits and Connection of Unused Pins ...
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Memory Space The PD78F9500, 78F9501, 78F9502 can access memory space. Figures 3-1 to 3-3 show the memory maps Special function registers ...
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Internal high-speed RAM Data memory space ...
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Figure 3-3. Memory Map ( PD78F9502 Special function registers Internal high-speed RAM Data memory space ...
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Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The PD78F9500, 78F9501, 78F9502 provide the following internal ROMs (or flash memory) containing the following ...
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Internal data memory space 128-byte internal high-speed RAM is provided in the PD78F9500, 78F9501, 78F9502. The internal high-speed RAM can also be used as a stack memory. 3.1.3 Special function register (SFR) area Special function registers (SFRs) of on-chip ...
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Figure 3-5. Data Memory Addressing ( PD78F9501 Special function registers (SFR) 256 8 bits Internal ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Data Memory Addressing ( PD78F9502 Special function registers (SFR) 256 8 bits ...
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Processor Registers The PD78F9500, 78F9501, 78F9502 provide the following on-chip processor registers. 3.2.1 Control registers The control registers have special functions to control the program sequence statuses and stack memory. The control registers include a program counter, a program ...
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CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls interrupt request acknowledge operations of the CPU. When the interrupt disabled (DI) status is set. All interrupt requests are disabled. When the ...
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Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area (Other than the internal high-speed RAM area cannot ...
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General-purpose registers A general-purpose register consists of eight 8-bit registers ( and H). In addition each register being used as an 8-bit register, two 8-bit registers in pairs can be used as a ...
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Special function registers (SFRs) Unlike the general-purpose registers, each special function register has a special function. The special function registers are allocated to the 256-byte area FF00H to FFFFH. The special function registers can be manipulated, like the general-purpose ...
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Table 3-3. Special Function Registers (1/3) Symbol Special Function Register (SFR) Name 7 6 FF00H, FF01H 0 0 FF02H FF03H P3 P47 P46 P45 FF04H P4 FF05H to FF0DH FF0EH CMP01 FF0FH CMP11 FF10H, FF11H 1 1 ...
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Table 3-3. Special Function Registers (2/3) Symbol Special Function Register (SFR) Name <LVI 0 0 FF50H LVIM ON> FF51H LVIS FF52H, FF53H FF54H RESF FF55H to FF57H FF58H ...
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Table 3-3. Special Function Registers (3/3) Symbol Special Function Register (SFR) Name FFA5H FLAPH FFA6H FLAPH FFA7H FLAPLC FLAP FLAP FLAP FFA8H FLW FLW7 FLW6 FLW5 FLW4 ...
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Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time ...
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Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) to branch. This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed. CALL !addr16 and BR !addr16 instructions ...
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Register addressing [Function] The register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) to branch. This function is carried out when the BR AX instruction is executed. [Illustration ...
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Operand Address Addressing The following methods (addressing) are available to specify the register and memory to undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand ...
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Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with the 8-bit data in an instruction word. The fixed space where this addressing is applied is the 160-byte space FE80H to FF1FH ...
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Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with the 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space FF00H to FFFFH. However, SFRs mapped at FF00H ...
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Register addressing [Function] A general-purpose register is accessed as an operand. The general-purpose register to be accessed is specified with the register specify code and functional name in the instruction code. Register addressing is carried out when an instruction ...
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Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register pair specify code in the instruction code. This addressing ...
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Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as ...
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Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon interrupt ...
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... CHAPTER 2 PIN FUNCTIONS. Port 4 Pin Name I/O P20 I/O Port 2. 4-bit I/O port. P21 Can be set to input or output mode in 1-bit units. P22 On-chip pull-up resistor can be connected by setting software. Note P23 P32 I/O Port 3 On-chip pull-up resistor can be connected by Note P34 setting software ...
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... Port 4-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 2 (PM2). When the P20 to P23 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 2 (PU2). This port can also be used for timer I/O, and external interrupt request input. ...
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Figure 4-2. Block Diagram of P20 and P21 WR PU PU2 PU20, PU21 Alternate RD function WR PORT P2 Output latch (P20, P21 PM2 PM20, PM21 Alternate function P2: Port register 2 PU2: Pull-up resistor option register 2 ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P22 WR PU PU2 PU22 RD WR PORT P2 Output latch (P22 PM2 PM22 P2: Port register 2 PU2: Pull-up resistor option register 2 PM2: Port mode register 2 ...
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WR PU PU2 PU23 RD WR PORT P2 Output latch (P23 PM2 PM23 P2: Port register 2 PU2: Pull-up resistor option register 2 PM2: Port mode register 2 RD: Read signal WR : Write signal 52 CHAPTER 4 ...
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... The P32 pin is a 1-bit I/O port with an output latch. This pin can be set to the input or output mode by using port mode register 3 (PM3). When this pin is used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 3 (PU3). This pin can also be used for external interrupt request input. ...
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... Port 2-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 4 (PM4). When the P40 and P43 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 4 (PU4). Reset signal generation sets port 4 to the input mode. ...
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Figure 4-7. Block Diagram of P40 and P43 WR PU PU4 PU40, PU43 RD WR PORT P4 Output latch (P40, P43 PM4 PM40, PM43 P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register ...
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Port mode registers (PM2 to PM4) These registers are used to set the corresponding port to the input or output mode in 1-bit units. Each port mode register can be set by a 1-bit or 8-bit memory manipulation instruction. ...
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... Port registers (P2 to P4) These registers are used to write data to be output from the corresponding port pin to an external device connected to the chip. When a port register is read, the pin level is read in the input mode, and the value of the output latch of the port is read in the output mode. ...
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... Pull-up resistor option registers (PU2 to PU4) These registers are used to specify whether an on-chip pull-up resistor is connected to P20 to P23, P32, P34, P40 and P43. By setting PU2 to PU4, an on-chip pull-up resistor can be connected to the port pin corresponding to the bit of PU2 to PU4. PU2 to PU4 are set by using a 1-bit or 8-bit memory manipulation instruction. ...
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Operation of Port Function The operation of a port differs, as follows, depending on the setting of the I/O mode. Caution Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in 8-bit units. Therefore, the ...
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CHAPTER 5 CLOCK GENERATORS 5.1 Functions of Clock Generators The clock generators include a circuit that generates a clock (system clock supplied to the CPU and peripheral hardware, and a circuit that generates a clock (interval time generation ...
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Configuration of Clock Generators The clock generators consist of the following hardware. Table 5-1. Configuration of Clock Generators Item Control registers Processor clock control register (PCC) Preprocessor clock control register (PPCC) Low-speed internal oscillation mode register (LSRCM) Oscillators High-speed ...
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Figure 5-1. Block Diagram of Clock Generators STOP System clock Note oscillator EXCLK/P23 External clock input f X High-speed internal oscillation Option byte 1: Cannot be stopped. 0: Can be stopped. Low-speed internal oscillation mode register (LSRCM) Internal bus Note ...
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Registers Controlling Clock Generators The clock generators are controlled by the following three registers. Processor clock control register (PCC) Preprocessor clock control register (PPCC) Low-speed internal oscillation mode register (LSRCM) (1) Processor clock control register (PCC) and preprocessor clock ...
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The fastest instruction of the PD78F9500, 78F9501, 78F9502 is executed in two CPU clocks. Therefore, the relationship between the CPU clock (f Table 5-2. Relationship between CPU Clock and Minimum Instruction Execution Time Note CPU Clock (f ) CPU f ...
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System Clock Oscillators The following three types of system clock oscillators are available. High-speed internal oscillator: External clock input circuit: 5.4.1 High-speed internal oscillator The PD78F9500, 78F9501, 78F9502 include a high-speed internal oscillator (8 MHz (TYP.)). If the high-speed ...
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Operation of CPU Clock Generator A clock ( supplied to the CPU from the system clock (f CPU oscillators. High-speed internal oscillator: External clock input circuit: The system clock oscillator is selected by the option byte. For ...
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CHAPTER 5 CLOCK GENERATORS (a) The internal reset signal is generated by the power-on clear function on power application, the option byte is referenced after reset, and the system clock is selected. (b) The option byte is referenced and the ...
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External clock input circuit If external clock input is selected by the option byte, the following is possible. High-speed operation The accuracy of processing is improved as compared with high-speed internal oscillation (8 MHz (TYP.)) because an oscillation frequency ...
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CHAPTER 5 CLOCK GENERATORS Figure 5-9. Status Transition of Default Start by External Clock Input Interrupt HALT Remark PCC: Processor clock control register PPCC: Preprocessor clock control register Preliminary User’s Manual U18681EJ1V0UD Power application V > 2.1 V 0.1 V ...
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Operation of Clock Generator Supplying Clock to Peripheral Hardware The following two types of clocks are supplied to the peripheral hardware. Clock to peripheral hardware (f XP Low-speed internal oscillation clock (f (1) Clock to peripheral hardware The clock ...
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Figure 5-10. Status Transition of Low-Speed Internal Oscillator Can be stopped Clock source of WDT is selected Note by software Low-speed internal oscillator can be stopped LSRSTOP = 1 Low-speed internal oscillator stops Note The clock source of the watchdog ...
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Functions of 8-Bit Timer H1 8-bit timer H1 has the following functions. Interval timer PWM output mode Square-wave output 6.2 Configuration of 8-Bit Timer H1 8-bit timer H1 consists of the following hardware. Item Timer register 8-bit timer counter ...
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H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 3 2 Decoder ...
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H compare register 01 (CMP01) This register can be read or written by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 6-2. Format of 8-Bit Timer H Compare Register 01 (CMP01) ...
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Registers Controlling 8-Bit Timer H1 The following three registers are used to control 8-Bit Timer H1. 8-bit timer H mode register 1 (TMHMD1) Port mode register 2 (PM2) Port register 2 (P2) (1) 8-bit timer H mode register 1 ...
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Figure 6-4. Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Address: FF70H After reset: 00H <7> Symbol TMHMD1 TMHE1 TMHE1 0 Stop timer count operation (counter is cleared Enable timer count operation (count operation started by ...
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Port mode register 2 (PM2) When using the P20/TOH1 pin for timer output, clear PM20, the output latch of P20 to 0. PM2 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM2 ...
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Usage Generates the INTTMH1 signal repeatedly at the same interval. <1> Set each register. Figure 6-6. Register Setting During Interval Timer/Square-Wave Output Operation (i) Setting timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 TMHMD1 0 0/1 0/1 (ii) ...
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Figure 6-7. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation (01H Count clock Count start 00H 01H 8-bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 <1> <1> The count operation is enabled by setting the TMHE1 bit to ...
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Figure 6-7. Timing of Interval Timer/Square-Wave Output Operation (2/2) Count clock Count start 00H 01H 8-bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 Count clock Count start 8-bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 Interval time 80 CHAPTER 6 ...
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Operation as PWM output mode In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 01 (CMP01) controls the cycle of timer output (TOH1). Rewriting the CMP01 register during ...
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When 8-bit timer counter H1 and the CMP11 register match, TOH1 output becomes inactive and the compare register to be compared with 8-bit timer counter H1 is changed from the CMP11 register to the CMP01 register. At this time, ...
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Figure 6-9. Operation Timing in PWM Output Mode (1/4) (a) Basic operation (00H < CMP11 < CMP01 < FFH) Count clock 8-bit timer counter H1 00H 01H CMP01 CMP11 TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) <1> TOH1 (TOLEV1 = 1) ...
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Figure 6-9. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP01 = FFH, CMP11 = 00H Count clock 8-bit timer counter H1 00H 01H CMP01 CMP11 TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) (c) Operation when CMP01 = FFH, ...
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CHAPTER 6 8-BIT TIMER H1 Figure 6-9. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP01 = 01H, CMP11 = 00H Count clock 00H 01H 00H 01H 00H 8-bit timer counter H1 CMP01 CMP11 TMHE1 INTTMH1 TOH1 (TOLEV1 ...
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Figure 6-9. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP11 (CMP11 = 02H Count clock 8-bit timer counter H1 00H 01H 02H CMP01 01H CMP11 TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) <1> <1> The count operation ...
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Functions of Watchdog Timer The watchdog timer is used to detect an inadvertent program loop program loop is detected, an internal reset signal is generated. When a reset occurs due to the watchdog timer, bit 4 (WDTRF) ...
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Table 7-2. Option Byte Setting and Watchdog Timer Operation Mode Low-Speed Internal Oscillator Cannot Be Stopped Low-Speed Internal Oscillator Can Be Stopped by Software Note 1 Watchdog timer clock Fixed source Operation after reset Operation starts ...
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Configuration of Watchdog Timer The watchdog timer consists of the following hardware. Table 7-3. Configuration of Watchdog Timer Item Control registers Figure 7-1. Block Diagram of Watchdog Timer 2 Clock 16-bit input counter ...
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Registers Controlling Watchdog Timer The watchdog timer is controlled by the following two registers. Watchdog timer mode register (WDTM) Watchdog timer enable register (WDTE) (1) Watchdog timer mode register (WDTM) This register sets the overflow time and operation clock ...
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Cautions 2. After reset is released, WDTM can be written only once by an 8-bit memory manipulation instruction. If writing is attempted a second time, an internal reset signal is generated. However, at the first write, if “1” and “x” ...
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Operation of Watchdog Timer 7.4.1 Watchdog timer operation when “low-speed internal oscillator cannot be stopped” is selected by option byte The operation clock of watchdog timer is fixed to low-speed internal oscillation clock. After reset is released, operation is ...
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CHAPTER 7 WATCHDOG TIMER Figure 7-4. Status Transition Diagram When “Low-Speed Internal Oscillator Cannot Be Stopped” Is Selected by Option Byte WDT clock: f Overflow time: 546.13 ms (MAX.) WDTE = “ACH” Clear WDT counter. WDT clock: f Overflow time: ...
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Watchdog timer operation when “low-speed internal oscillator can be stopped by software” is selected by option byte The operation clock of the watchdog timer can be selected as either the low-speed internal oscillation clock or system clock. After reset ...
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Figure 7-5. Status Transition Diagram When “Low-Speed Internal Oscillator Can Be Stopped by Software” Is Selected by Option Byte WDT clock = f X Select overflow time (settable only once). WDTE = “ACH” Clear WDT counter. WDT clock ...
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Watchdog timer operation in STOP mode (when “low-speed internal oscillator can be stopped by software” is selected by option byte) The watchdog timer stops counting during STOP instruction execution regardless of whether the system clock or low-speed internal oscillation ...
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Watchdog timer operation in HALT mode (when “low-speed internal oscillator can be stopped by software” is selected by option byte) The watchdog timer stops counting during HALT instruction execution regardless of whether the operation clock of the watchdog timer ...
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CHAPTER 8 INTERRUPT FUNCTIONS 8.1 Interrupt Function Types There are two types of interrupts: maskable interrupts and resets. Maskable interrupts These interrupts undergo mask control. When an interrupt request occurs, the standby release signal occurs, and if an interrupt can ...
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Figure 8-1. Basic Configuration of Interrupt Function (A) Internal maskable interrupt IF Interrupt request (B) External maskable interrupt External interrupt mode register (INTM0) Edge Interrupt detector request IF: Interrupt request flag IE: Interrupt enable flag MK: Interrupt mask flag CHAPTER ...
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Interrupt Function Control Registers The interrupt functions are controlled by the following four types of registers. • Interrupt request flag register 0 (IF0) • Interrupt mask flag register 0 (MK0) • External interrupt mode register 0 (INTM0) • Program ...
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Interrupt mask flag register 0 (MK0) The interrupt mask flag is used to enable and disable the corresponding maskable interrupts. MK0 is set with a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets MK0 to FFH. Figure ...
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Cautions 2. Before setting the INTM0 register, be sure to set the corresponding interrupt mask flag ( disable interrupts. After setting the INTM0 register, clear the interrupt request flag ( interrupts. (4) Program status word (PSW) ...
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Figure 8-6 shows the algorithm of interrupt request acknowledgment. When a maskable interrupt request is acknowledged, the contents of the PSW and PC are saved to the stack in that order, the IE flag is reset to 0, and the ...
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Figure 8-8. Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Set at Last Clock During Instruction Execution) Clock CPU NOP Interrupt If an interrupt request flag ( IF) is set at the last clock of the instruction, the interrupt ...
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Figure 8-9. Example of Multiple Interrupts (1/2) Example 1. Multiple interrupts are acknowledged Main processing INTxx During interrupt INTxx servicing, interrupt request INTyy is acknowledged, and multiple interrupts are generated. Before each interrupt request acknowledgement, the ...
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Figure 8-9. Example of Multiple Interrupts (2/2) Example 3. A priority is controlled by the Multiple interrupts The vector interrupt enable state is set for INTP0, INTP1, and INTTMH1. (Interruption priority INTP0 > INTP1 > INTTMH1 (refer to Table8-1)) Main ...
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Standby Function and Configuration 9.1.1 Standby function Table 9-1. Relationship Between Operation Clocks in Each Operation Status Status Note 1 Operation Mode Reset Stopped STOP Oscillating HALT Notes 1. When “Cannot be stopped” is selected for low-speed internal oscillator ...
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STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the system clock oscillator stops, stopping the whole system, thereby considerably reducing the CPU operating current. Because this mode can be cleared by an interrupt request, ...
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Standby Function Operation 9.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. The operating statuses in the HALT mode are shown below. Caution Because an interrupt request signal is used to clear ...
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HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgement is enabled, vectored interrupt ...
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Table 9-3. Operation in Response to Interrupt Request in HALT Mode Release Source Maskable interrupt request Reset signal generation : don’t care 9.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the ...
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STOP mode release Figure 9-3. Operation Timing When STOP Mode Is Released STOP mode is released. STOP mode System clock oscillation CPU clock Operation Note stops Note The operation stop time (MIN.), 34 s (TYP.), and ...
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CHAPTER 9 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is input, STOP mode is released and a reset operation is performed after the oscillation stabilization time has elapsed. Figure 9-5. STOP Mode Release by Reset ...
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The following four operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer overflows (3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit ...
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Figure 10-1. Block Diagram of Reset Function Set Reset signal of WDT RESET Reset signal of POC Reset signal of LVI Caution The LVI circuit is not reset by the internal reset signal of the LVI circuit. Remarks 1. LVIM: ...
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Figure 10-3. Timing of Reset by Overflow of Watchdog Timer High-speed internal oscillation clock or external clock input Normal operation CPU clock Watchdog overflow Internal reset signal Port pin Note The operation stop time is 277 s (MIN.), 544 s ...
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Table 10-1. Hardware Statuses After Reset Acknowledgment Hardware Note 1 Program counter (PC) Stack pointer (SP) Program status word (PSW) RAM Data memory General-purpose registers Ports (P2 to P4) (output latches) Port mode registers (PM2 to PM4) Pull-up resistor option ...
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Notes 3. These values change as follows depending on the reset source. Reset Source Register RESF WDTRF LVIRF LVIM LVIS 10.1 Register for Confirming Reset Source Many internal reset generation sources exist in the register (RESF) is used to store ...
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CHAPTER 11 POWER-ON-CLEAR CIRCUIT 11.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) has the following functions. Generates internal reset signal at power on. Compares supply voltage (V DD when V < POC Compares supply voltage (V ...
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Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 11-1. Figure 11-1. Block Diagram of Power-on-Clear Circuit V DD Reference voltage source 11.3 Operation of Power-on-Clear Circuit In the power-on-clear circuit, the supply ...
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Cautions for Power-on-Clear Circuit In a system where the supply voltage (V voltage (V ), the system may be repeatedly reset and released from the reset status. In this case, the time from POC release of reset to the ...
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Figure 11-3. Example of Software Processing After Release of Reset (2/2) Checking reset cause Check reset source WDTRF of RESF register = 1? No LVIRF of RESF register = 1? No Power-on clear/external reset generated 122 CHAPTER 11 POWER-ON-CLEAR CIRCUIT ...
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CHAPTER 12 LOW-VOLTAGE DETECTOR 12.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) has following functions. Compares supply voltage (V DD internal reset signal when V DD Detection levels (ten levels) of supply voltage can be changed by software. Interrupt ...
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Registers Controlling Low-Voltage Detector The low-voltage detector is controlled by the following registers. Low-voltage detect register (LVIM) Low-voltage detection level select register (LVIS) (1) Low-voltage detect register (LVIM) This register sets low-voltage detection and the operation mode. This register ...
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Low-voltage detection level select register (LVIS) This register selects the low-voltage detection level. This register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H Figure 12-3. Format of Low-Voltage Detection Level ...
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Operation of Low-Voltage Detector The low-voltage detector can be used in the following two modes. Used as reset Compares the supply voltage (V V < and releases internal reset when V DD LVI Used as interrupt Compares ...
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Figure 12-4. Timing of Low-Voltage Detector Internal Reset Signal Generation Supply voltage ( LVI detection voltage (V ) LVI POC detection voltage (V ) POC <2> LVIMK flag H (set by software) <1> Note 1 LVION flag (set ...
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When used as interrupt When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bits (LVIS3 to LVIS0) of the low-voltage detection level select register (LVIS). <3> Set bit ...
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Figure 12-5. Timing of Low-Voltage Detector Interrupt Signal Generation Supply voltage ( LVI detection voltage (V ) LVI POC detection voltage (V ) POC <2> LVIMK flag (set by software) <1> Note 1 <7> Cleared by software LVION ...
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Cautions for Low-Voltage Detector In a system where the supply voltage ( the operation is as follows depending on how the low-voltage detector is used. LVI <1> When used as reset The system may be repeatedly reset ...
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CHAPTER 12 LOW-VOLTAGE DETECTOR Figure 12-6. Example of Software Processing After Release of Reset (1/2) If supply voltage fluctuation less in vicinity of LVI detection voltage Reset Initialization processing <1> LVI reset Setting LVI Setting 8-bit ...
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Figure 12-6. Example of Software Processing After Release of Reset (2/2) Checking reset source Check reset source WDTRF of RESF register = 1? LVIRF of RESF register = 1? Reset processing by low-voltage detector 132 CHAPTER 12 LOW-VOLTAGE DETECTOR Yes ...
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Functions of Option Byte The address 0080H of the flash memory of the PD78F9500, 78F9501, 78F9502 is an option byte area. When power is supplied or when starting after a reset, the option byte is automatically referenced, and settings ...
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Format of Option Byte Format of option bytes is shown below. Address: 0080H ENPU34 1 On-chip pull-up resistor on RESET pin is selected. 0 On-chip pull-up resistor on RESET pin is not selected. Remark When ...
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... RESET pin is used as an input-only port pin (P34)" by the option byte function. Before supplying power to the target system, connect a dedicated flash memory programmer and turn its power on. If the power is supplied to the target system beforehand, it cannot be switched to the flash memory programming mode ...
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Features The internal flash memory of the PD78F9500, 78F9501, 78F9502 has the following features. Erase/write even without preparing a separate dedicated power supply Capacity: 1/2/4 KB Erase unit: 1 block (256 bytes) Write unit: 1 block (at onboard/offboard programming ...
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Memory Configuration The 1/2/4 KB internal flash memory area is divided into 4/8/16 blocks and can be programmed/erased in block units. All the blocks can also be erased at once, by using a dedicated flash memory programmer. FFFFH Special ...
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... Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer. (1) On-board programming The contents of the flash memory can be rewritten after the mounted on the target system. The connectors that connect the dedicated flash memory programmer must be mounted on the target system. (2) Off-board programming Data can be written to the flash memory with a dedicated program adapter (FA series) before the PD78F9500, 78F9501, 78F9502 are mounted on the target system ...
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... Note DGCLK is a clock for communication, while DGDATA is a transmit/receive signal for communication data. A host machine that controls the dedicated flash memory programmer is necessary. When using the PG-FP4 or FL-PR4, data can be written with just the dedicated flash memory programmer after downloading the program from the host machine ...
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... EXCLK pin The EXCLK pin is used as the serial interface of flash memory programming. Therefore, if the EXCLK pin is connected to an external device, a signal conflict occurs. To prevent the conflict of signals, isolate the connection with the external device. When connected a capacitor to the EXCLK pin, waveform at the time of communication is changed. Therefore there is a possibility that cannot communicate depending on capacitor capacitance ...
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... RESET pin If the reset signal of the dedicated flash memory programmer is connected to the RESET pin that is connected to the reset signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the reset signal generator. If the reset signal is input from the user system while the flash memory programming mode is set, the flash memory will not be correctly programmed ...
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... To rewrite the contents of the flash memory by using the dedicated flash memory programmer, set the PD78F9500, 78F9501, 78F9502 in the flash memory programming mode. 78F9502 are connected to the flash memory programmer and a communication command is transmitted to the microcontroller, the microcontroller is set in the flash memory programming mode. ...
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Command Name ACK NAK 14.7.3 Security settings The operations shown below can be prohibited using the security setting command. Batch erase (chip erase) is prohibited Execution of the block erase and batch erase (chip erase) commands for entire blocks in ...
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Table 14-6 shows the relationship between the security setting and the operation in each programming mode. Table 14-6. Relationship Between Security Setting and Operation In Each Programming Mode Programming Mode Security Setting Batch erase (chip erase) Block erase Write Notes ...
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Figure 14-6. Block Diagram of Self Programming Flash programming command Protect byte register (FLCMD) PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 FLCMD2 FLCMD1 FLCMD0 5 3 Increment circuit Flash address pointer H (FLAPH) Match Flash address pointer L (FLAPL) Match Flash address ...
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Figure 14-7. Self Programming State Transition Diagram User program Normal mode Specific sequence Self programming mode Self programming command completion/error Flash memory control block (hardware) Self programming command under execution Flash memory Table 14-8. Self Programming Controlling Commands Command Name ...
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Cautions on self programming function No instructions can be executed while a self programming command is being executed. Therefore, clear and restart the watchdog timer counter in advance so that the watchdog timer does not overflow during self programming. ...
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This register is set with an 8-bit memory manipulation instruction. Reset signal generation makes the contents of this register undefined. Figure 14-8. Format of Flash Programming Mode Control Register (FLPMC) Address: FFA2H After reset: Undefined Symbol 7 6 FLPMC 0 ...
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Write the inverted value of the value to be set to bit 0 (FLSPM) of the FLPMC (writing in this step is invalid) <4> Write the value to be set to bit 0 (FLSPM) of the FLPMC (writing in ...
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If a value other than the inverted value of the value to be set to FLPMC is written by the first store instruction after <2> If the first store instruction operation after <3> peripheral register other than ...
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Flash programming command register (FLCMD) This register is used to specify whether the flash memory is erased, written, or verified in the self-programming mode. This register is set by using a 1-bit or 8-bit memory manipulation instruction. Reset signal ...
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Flash address pointers H and L (FLAPH and FLAPL) These registers are used to specify the start address of the flash memory when the memory is erased, written, or verified in the self-programming mode. FLAPH and FLAPL consist of ...
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Flash write buffer register (FLW) This register is used to store the data to be written to the flash memory. This register is set with an 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure ...
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Figure 14-19. Format of Protect Byte (2/2) PD78F9502 PRSELF4 PRSELF3 PRSELF2 Other than above 14.8.4 Example of shifting normal mode to self ...
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Figure 14-16. Example of Shifting to Self Programming Mode Shift to self programming mode <1> Disable interrupts (by setting MK0 to FFH and executing DI instruction) FLPMC = 01H (set value) <4> FLPMC = 0FEH (inverted set value) FLPMC = ...
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An example of the program that shifts the mode to self programming mode is shown below. ;---------------------------- ;START ;---------------------------- MOV MK0,#11111111B MOV FLCMD,#00H DI ModeOnLoop: MOV PFS,#00H MOV PFCMD,#0A5H MOV FLPMC,#01H MOV FLPMC,#0FEH MOV FLPMC,#01H NOP HALT BT PFS.0,$ModeOnLoop ;---------------------------- ...
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Example of shifting self programming mode to normal mode The operating mode must be returned from self programming mode to normal mode after performing self programming. An example of shifting to normal mode is explained below. <1> Clear FLCMD ...
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Figure 14-17. Example of Shifting to Normal Mode <1> Clear FLCMD (FLCMD=00H) <3> FLPMC = 0FFH (inverted set value) <4> Check execution result Caution Be sure to perform the series of operations described above using the user program at an ...
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An example of a program that shifts the mode to normal mode is shown below. ;---------------------------- ;START ;---------------------------- MOV FLCMD,#00H ModeOffLoop: MOV PFS,#00H MOV PFCMD,#0A5H MOV FLPMC,#00H MOV FLPMC,#0FFH MOV FLPMC,#00H BT PFS.0,$ModeOffLoop MOV MK0,#INT_MK0 EI ;---------------------------- ;END ;---------------------------- CHAPTER ...
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Example of block erase operation in self programming mode An example of the block erase operation in self programming mode is explained below. <1> Set 03H (block erase) to the flash program command register (FLCMD). <2> Set the block ...
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Figure 14-18. Example of Block Erase Operation in Self Programming Mode Block erasure <1> Set erase command (FLCMD = 03H) <2> Set no. of block to be erased to FLAPH <3> Set FLAPL to 00H <4> Set the same value ...
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An example of a program that performs a block erase in self programming mode is shown below. ;---------------------------- ;START ;---------------------------- FlashBlockErase: MOV FLCMD,#03H MOV FLAPH,#07H MOV FLAPL,#00H MOV FLAPHC,#07H MOV FLAPLC,#00H MOV PFS,#00H MOV WDTE,#0ACH HALT MOV A,PFS MOV CmdStatus,A ...
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Example of block blank check operation in self programming mode An example of the block blank check operation in self programming mode is explained below. <1> Set 04H (block blank check) to the flash program command register (FLCMD). <2> ...
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Figure 14-19. Example of Block Blank Check Operation in Self Programming Mode Block blank check <1> Set block blank check command (FLCMD = 04H) <2> Set no. of block for blank check to FLAPH <3> Set FLAPL to 00H <4> ...
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An example of a program that performs a block blank check in self programming mode is shown below. ;---------------------------- ;START ;---------------------------- FlashBlockBlankCheck: MOV FLCMD,#04H MOV FLAPH,#07H MOV FLAPL,#00H MOV FLAPHC,#07H MOV FLAPLC,#0FFH MOV PFS,#00H MOV WDTE,#0ACH HALT MOV A,PFS MOV ...
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Example of byte write operation in self programming mode An example of the byte write operation in self programming mode is explained below. <1> Set 05H (byte write) to the flash program command register (FLCMD). <2> Set the number ...
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Figure 14-20. Example of Byte Write Operation in Self Programming Mode Byte write <1> Set byte write command (FLCMD = 05H) <2> Set no. of block to be written, to FLAPH <3> Set address at which data ...
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An example of a program that performs a byte write in self programming mode is shown below. ;---------------------------- ;START ;---------------------------- FlashWrite: MOV FLCMD,#05H MOV FLAPH,#07H MOV FLAPL,#20H MOV FLW,#10H MOV PFS,#00H MOV WDTE,#0ACH HALT MOV A,PFS MOV CmdStatus,A ;---------------------------- ;END ...
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Example of internal verify operation in self programming mode An example of the internal verify operation in self programming mode is explained below. Internal verify 1 <1> Set 01H (internal verify 1) to the flash program command register (FLCMD). ...
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Figure 14-21. Example of Internal Verify Operation in Self Programming Mode Internal verify 1 <1> Set internal verify 1 command (FLCMD = 01H) <2> Set No. of block for internal verify, to FLAPH <3> Sets FLAPL to 00H <4> Set ...
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Figure 14-22. Example of Internal Verify Operation in Self Programming Mode Internal verify 2 <1> Set internal verify 2 command (FLCMD = 02H) <2> Set No. of block for internal verify, to FLAPH <3> Sets FLAPL to the start address ...
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An example of a program that performs an internal verify in self programming mode is shown below. Internal verify 1 ;---------------------------- ;START ;---------------------------- FlashVerify: MOV FLCMD,#01H MOV FLAPH,#07H MOV FLAPL,#00H MOV FLAPHC,#07H MOV FLAPLC,#FFH MOV PFS,#00H MOV WDTE,#0ACH HALT MOV ...
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Examples of operation when command execution time should be minimized in self programming mode Examples of operation when the command execution time should be minimized in self programming mode are explained below. (1) Erasure to blank check <1> Mode ...
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An example of a program when the command execution time (from erasure to black check) should be minimized in self programming mode is shown below. ;--------------------------------------------------------------------- ;START ;--------------------------------------------------------------------- MOV MK0,#11111111B MOV FLCMD,#00H DI ModeOnLoop: MOV PFS,#00H MOV PFCMD,#0A5H MOV FLPMC,#01H ...
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MOV FLAPLC,#0FFH MOV WDTE,#0ACH HALT MOV A,PFS CMP A,#00H BNZ $StatusError MOV FLCMD,#00H ModeOffLoop: MOV PFS,#00H MOV PFCMD,#0A5H MOV FLPMC,#00H MOV FLPMC,#0FFH MOV FLPMC,#00H BT PFS.0,$ModeOffLoop MOV MK0,#INT_MK0 EI BR StatusNormal ;--------------------------------------------------------------------- ;END (abnormal termination processing); Perform processing to shift ...
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Write to internal verify <1> Mode is shifted from normal mode to self programming mode (<1> to <7> in 14.8.4) <2> Specification of source data for write <3> Execution of byte write <4> <3> is repeated until all data ...
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An example of a program when the command execution time (from write to internal verify) should be minimized in self programming mode is shown below. ;--------------------------------------------------------------------- ;START ;--------------------------------------------------------------------- MOV MK0,#11111111B MOV FLCMD,#00H DI ModeOnLoop: MOV PFS,#00H MOV PFCMD,#0A5H MOV FLPMC,#01H ...
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INCW DE BR FlashWriteLoop FlashVerify: MOVW HL,#WriteAdr MOV FLCMD,#02H MOV A,H MOV FLAPH,A MOV A,L MOV FLAPL,A MOV A,D MOV FLAPHC,A MOV A,E MOV FLAPLC,A MOV WDTE,#0ACH HALT MOV A,PFS CMP A,#00H BNZ $StatusError MOV FLCMD,#00H ModeOffLoop: MOV PFS,#00H MOV ...
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StatusNormal: ;--------------------------------------------------------------------- ; Data to be written ;--------------------------------------------------------------------- DataAdrTop: DB XXH DB XXH DB XXH DB XXH : : DB XXH DataAdrBtm: ;--------------------------------------------------------------------- Remark Internal verify 2 is used in the above program example. ...
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Figure 14-25. Example of Operation When Interrupt-Disabled Time Should Be Minimized Figure 14-18 <1> Specify block erase command <1> to <5> <2> Shift to self programming Figure 14-16 <1> to <7> <3> Execute block erase command Figure 14-18 <6> to ...
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An example of a program when the interrupt-disabled time (from erasure to blank check) should be minimized in self programming mode is shown below. ;--------------------------------------------------------------------- ;START ;--------------------------------------------------------------------- FlashBlockErase: ; Sets erase command MOV FLCMD,#03H MOV FLAPH,#07H MOV FLAPL,#00H MOV FLAPHC,#07H ...
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CALL !ModeOff BR StatusNormal ;--------------------------------------------------------------------- ;END (abnormal termination processing); Perform processing to shift to normal mode in order to return to normal processing ;--------------------------------------------------------------------- StatusError: ;--------------------------------------------------------------------- ;END (normal termination processing) ;--------------------------------------------------------------------- StatusNormal: ;--------------------------------------------------------------------- ;Processing to shift to self programming mode ...
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CHAPTER 14 FLASH MEMORY MOV FLPMC,#00H ; FLPMC register control (sets value) MOV FLPMC,#0FFH ; FLPMC register control (inverts set value) MOV FLPMC,#00H ; Sets normal mode via FLPMC register control (sets value) BT PFS.0,$ModeOffLoop ; Checks completion of write ...
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Write to internal verify <1> Specification of source data for write <2> Specification of byte write command (<1> to <4> in 14.8.8) <3> Mode is shifted from normal mode to self programming mode (<1> to <7> in 14.8.4) <4> ...
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Figure 14-26. Example of Operation When Interrupt-Disabled Time Should Be Minimized Figure 14-20 <1> to <4> Figure 14-16 <1> to <7> Figure 14-20 <5> to <10> Figure 14-17 <1> to <6> Figure 14-21 <7> Specify internal verify command <1> to ...
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An example of a program when the interrupt-disabled time (from write to internal verify) should be minimized in self programming mode is shown below. ;--------------------------------------------------------------------- ;START ;--------------------------------------------------------------------- ; Sets write command FlashWrite: MOVW HL,#DataAdrTop ; Sets address at which data ...
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FlashVerify: MOVW HL,#WriteAdr MOV FLCMD,#02H MOV A,H MOV FLAPH,A MOV A,L MOV FLAPL,A MOV A,D MOV FLAPHC,A MOV A,E MOV FLAPLC,A CALL !ModeOn ; Execution of internal verify command MOV PFS,#00H MOV WDTE,#0ACH HALT MOV A,PFS CMP A,#00H BNZ $StatusError ...
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DI ModeOnLoop: MOV PFS,#00H MOV PFCMD,#0A5H MOV FLPMC,#01H MOV FLPMC,#0FEH MOV FLPMC,#01H NOP HALT BT PFS.0,$ModeOnLoop RET ;--------------------------------------------------------------------- ; Processing to shift to normal mode ;--------------------------------------------------------------------- ModeOff: MOV FLCMD,#00H MOV PFS,#00H MOV PFCMD,#0A5H MOV FLPMC,#00H MOV FLPMC,#0FFH MOV FLPMC,#00H BT ...
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DB XXH : : DB XXH DataAdrBtm: ;--------------------------------------------------------------------- Remark Internal verify 2 is used in the above program example. Use internal verify 1 to verify s whole block. CHAPTER 14 FLASH MEMORY Preliminary User’s Manual U18681EJ1V0UD 189 ...
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CHAPTER 15 INSTRUCTION SET OVERVIEW This chapter lists the instruction set of the PD78F9500, 78F9501, 78F9502. For details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series Instructions User’s Manual (U11047E). 15.1 Operation 15.1.1 ...
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CHAPTER 15 INSTRUCTION SET OVERVIEW 15.1.2 Description of “Operation” column A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair; ...
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CHAPTER 15 INSTRUCTION SET OVERVIEW 15.2 Operation List Mnemonic Operand MOV r, #byte saddr, #byte sfr, #byte Note Note saddr saddr sfr sfr !addr16 !addr16, A PSW, #byte A, ...
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CHAPTER 15 INSTRUCTION SET OVERVIEW Mnemonic Operand MOVW rp, #word AX, saddrp saddrp, AX Note AX, rp Note rp, AX Note XCHW AX, rp ADD A, #byte saddr, #byte saddr A, !addr16 A, [HL] A, [HL + ...
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CHAPTER 15 INSTRUCTION SET OVERVIEW Mnemonic Operand SUBC A, #byte saddr, #byte saddr A, !addr16 A, [HL] A, [HL + byte] AND A, #byte saddr, #byte saddr A, !addr16 A, [HL] A, [HL + ...
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CHAPTER 15 INSTRUCTION SET OVERVIEW Mnemonic Operand CMP A, #byte saddr, #byte saddr A, !addr16 A, [HL] A, [HL + byte] ADDW AX, #word SUBW AX, #word CMPW AX, #word INC r saddr DEC r saddr INCW ...
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CHAPTER 15 INSTRUCTION SET OVERVIEW Mnemonic Operand CALL !addr16 CALLT [addr5] RET RETI PUSH PSW rp POP PSW rp MOVW SP !addr16 $addr16 AX BC $saddr16 BNC $saddr16 BZ $saddr16 BNZ $saddr16 BT saddr.bit, $addr16 sfr.bit, ...
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CHAPTER 15 INSTRUCTION SET OVERVIEW 15.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand #byte A r 1st Operand ...
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CHAPTER 15 INSTRUCTION SET OVERVIEW (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand #word 1st Operand AX ADDW SUBW CMPW rp MOVW saddrp sp Note Only when rp = BC, DE, or HL. (3) ...
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CHAPTER 15 INSTRUCTION SET OVERVIEW (4) Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand 1st Operand Basic instructions Compound instructions (5) Other instructions RET, RETI, NOP, EI, DI, HALT, STOP AX !addr16 [addr5] BR CALL ...
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CHAPTER 16 ELECTRICAL SPECIFICATIONS (TARGET) Absolute Maximum Ratings ( Parameter Symbol Supply voltage Input voltage V I Output voltage V O Analog input voltage V AN Output current, high I OH Output ...