MC68HC711E9VFN2 Freescale Semiconductor, MC68HC711E9VFN2 Datasheet - Page 125

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MC68HC711E9VFN2

Manufacturer Part Number
MC68HC711E9VFN2
Description
IC MCU 12K OTP 2MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E9VFN2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
12KB (12K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Bit 5 — Unimplemented
MODF — Mode Fault Bit
Bits [3:0] — Unimplemented
8.7.3 Serial Peripheral Data I/O Register
The SPDR is used when transmitting or receiving data on the serial bus. Only a write to this register
initiates transmission or reception of a byte, and this only occurs in the master device. At the completion
of transferring a byte of data, the SPIF status bit is set in both the master and slave devices.
A read of the SPDR is actually a read of a buffer. To prevent an overrun and the loss of the byte that
caused the overrun, the first SPIF must be cleared by the time a second transfer of data from the shift
register to the read buffer is initiated.
SPI is double buffered in and single buffered out.
Freescale Semiconductor
Always reads 0
To clear the MODF bit, read the SPSR (with MODF set), then write to the SPCR. Refer to
Select
Always read 0
0 = No mode fault
1 = Mode fault
and
Address:
8.6 SPI System
Reset:
Read:
Write:
$102A
Figure 8-5. Serial Peripheral Data I/O Register (SPDR)
Bit 7
Bit 7
Errors.
Bit 6
6
M68HC11E Family Data Sheet, Rev. 5.1
Bit 5
5
Indeterminate after reset
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
SPI Registers
8.5.4 Slave
125

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