MC68HC11E1CFN2 Freescale Semiconductor, MC68HC11E1CFN2 Datasheet - Page 90

• Manufacturer Part Number: MC68HC11E1CFN2
• Description: IC MCU 512 EEPROM 2MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -

Resets and Interrupts
5.2.2 External Reset (RESET)
5.2.3 Computer Operating Properly (COP) Reset
Data Sheet
90
CAUTION:
The CPU distinguishes between internal and external reset conditions by sensing
whether the reset pin rises to a logic 1 in less than two E-clock cycles after an
internal device releases reset. When a reset condition is sensed, the RESET pin is
driven low by an internal device for four E-clock cycles, then released. Two E-clock
cycles later it is sampled. If the pin is still held low, the CPU assumes that an
external reset has occurred. If the pin is high, it indicates that the reset was initiated
internally by either the COP system or the clock monitor.
Do not connect an external resistor capacitor (RC) power-up delay circuit to the
reset pin of M68HC11 devices because the circuit charge time constant can cause
the device to misinterpret the type of reset that occurred.
The MCU includes a COP system to help protect against software failures. When
the COP is enabled, the software is responsible for keeping a free-running
watchdog timer from timing out. When the software is no longer being executed in
the intended sequence, a system reset is initiated.
The state of the NOCOP bit in the CONFIG register determines whether the COP
system is enabled or disabled. To change the enable status of the COP system,
change the contents of the CONFIG register and then perform a system reset. In
the special test and bootstrap operating modes, the COP system is initially
inhibited by the disable resets (DISR) control bit in the TEST1 register. The DISR
bit can subsequently be written to 0 to enable COP resets.
The COP timer rate control bits CR[1:0] in the OPTION register determine the COP
timeout period. The system E clock is divided by 2
factor shown in
timeout period. In normal operating modes, these bits can be written only once
within 64 bus cycles after reset.
CR[1:0]
0 0
0 1
1 0
1 1
Freescale Semiconductor, Inc.
E/2
Divide
For More Information On This Product,
E =
16
64
15
1
4
By
Table
– 0 ms, + 32.8 ms
XTAL = 4.0 MHz
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131.072 ms
32.768 ms
524.28 ms
Timeout
1.0 MHz
2.098 s
Resets and Interrupts
5-1. After reset, these bits are 0, which selects the fastest
Table 5-1. COP Timer Rate Select
– 0 ms, + 16.4 ms
XTAL = 8.0 MHz
16.384 ms
65.536 ms
262.14 ms
Timeout
2.0 MHz
1.049 s
XTAL = 12.0 MHz
– 0 ms, + 10.9 ms
15
and then further scaled by a
10.923 ms
43.691 ms
174.76 ms
699.05 ms
Timeout
3.0 MHz
M68HC11E Family — Rev. 5
XTAL = 16.0 MHz
– 0 ms, + 8.2 ms
Timeout
4.0 MHz
8.19 ms
32.8 ms
131 ms
524 ms
MOTOROLA