MC68HC11E1CFN2 Freescale Semiconductor, MC68HC11E1CFN2 Datasheet - Page 80

• Manufacturer Part Number: MC68HC11E1CFN2
• Description: IC MCU 512 EEPROM 2MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -

Central Processor Unit (CPU)
4.5.2 Direct
4.5.3 Extended
4.5.4 Indexed
4.5.5 Inherent
4.5.6 Relative
4.6 Instruction Set
Data Sheet
80
In the direct addressing mode, the low-order byte of the operand address is
contained in a single byte following the opcode, and the high-order byte of the
address is assumed to be $00. Addresses $00–$FF are thus accessed directly,
using 2-byte instructions. Execution time is reduced by eliminating the additional
memory access required for the high-order address byte. In most applications, this
256-byte area is reserved for frequently referenced data. In M68HC11 MCUs, the
memory map can be configured for combinations of internal registers, RAM, or
external memory to occupy these addresses.
In the extended addressing mode, the effective address of the argument is
contained in two bytes following the opcode byte. These are 3-byte instructions (or
4-byte instructions if a prebyte is required). One or two bytes are needed for the
opcode and two for the effective address.
In the indexed addressing mode, an 8-bit unsigned offset contained in the
instruction is added to the value contained in an index register (IX or IY). The sum
is the effective address. This addressing mode allows referencing any memory
location in the 64-Kbyte address space. These are 2- to 5-byte instructions,
depending on whether or not a prebyte is required.
In the inherent addressing mode, all the information necessary to execute the
instruction is contained in the opcode. Operations that use only the index registers
or accumulators, as well as control instructions with no arguments, are included in
this addressing mode. These are
1- or 2-byte instructions.
The relative addressing mode is used only for branch instructions. If the branch
condition is true, an 8-bit signed offset included in the instruction is added to the
contents of the program counter to form the effective branch address. Otherwise,
control proceeds to the next instruction. These are usually 2-byte instructions.
Refer to
addressing modes. For each instruction, the table shows the operand construction,
the number of machine code bytes, and execution time in CPU E-clock cycles.
Freescale Semiconductor, Inc.
Table
For More Information On This Product,
4-2, which shows all the M68HC11 instructions in all possible
Go to: www.freescale.com
Central Processor Unit (CPU)
M68HC11E Family — Rev. 5
MOTOROLA