MC68HC11E1CFN2 Freescale Semiconductor, MC68HC11E1CFN2 Datasheet - Page 117

• Manufacturer Part Number: MC68HC11E1CFN2
• Description: IC MCU 512 EEPROM 2MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -

7.1 Introduction
7.2 Data Format
7.3 Transmit Operation
M68HC11E Family — Rev. 5
MOTOROLA
Data Sheet — M68HC11E Family
The serial communications interface (SCI) is a universal asynchronous receiver
transmitter (UART), one of two independent serial input/output (I/O) subsystems in
the M68HC11 E series of microcontrollers. It has a standard non-return-to-zero
(NRZ) format (one start bit , eight or nine data bits, and one stop bit). Several baud
rates are available. The SCI transmitter and receiver are independent, but use the
same data format and bit rate.
All members of the E series contain the same SCI, with one exception. The SCI
system in the MC68HC11E20 and MC68HC711E20 MCUs have an enhanced SCI
baud rate generator. A divide-by-39 stage has been added that is enabled by an
extra bit in the BAUD register. This increases the available SCI baud rate
selections. Refer to
The serial data format requires these conditions:
Selection of the word length is controlled by the M bit of SCI control register
(SCCR1).
The SCI transmitter includes a parallel transmit data register (SCDR) and a serial
shift register. The contents of the serial shift register can be written only through
the SCDR. This double buffered operation allows a character to be shifted out
serially while another character is waiting in the SCDR to be transferred into the
1. An idle line in the high state before transmission or reception of a message
2. A start bit, logic 0, transmitted or received, that indicates the start of each
3. Data that is transmitted and received least significant bit (LSB) first
4. A stop bit, logic 1, used to indicate the end of a frame. A frame consists of a
5. A break, defined as the transmission or reception of a logic 0 for some
character
start bit, a character of eight or nine data bits, and a stop bit.
multiple number of frames
Freescale Semiconductor, Inc.
For More Information On This Product,
Section 7. Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
Go to: www.freescale.com
Figure 7-8
and
7.7.5 Baud Rate
Register.
Data Sheet
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