MC68HC11E1CFN2 Freescale Semiconductor, MC68HC11E1CFN2 Datasheet - Page 107

• Manufacturer Part Number: MC68HC11E1CFN2
• Description: IC MCU 512 EEPROM 2MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -

5.6 Low-Power Operation
5.6.1 Wait Mode
5.6.2 Stop Mode
M68HC11E Family — Rev. 5
MOTOROLA
Both stop mode and wait mode suspend CPU operation until a reset or interrupt
occurs. Wait mode suspends processing and reduces power consumption to an
intermediate level. Stop mode turns off all on-chip clocks and reduces power
consumption to an absolute minimum while retaining the contents of the entire
RAM array.
The WAI opcode places the MCU in wait mode, during which the CPU registers are
stacked and CPU processing is suspended until a qualified interrupt is detected.
The interrupt can be an external IRQ, an XIRQ, or any of the internally generated
interrupts, such as the timer or serial interrupts. The on-chip crystal oscillator
remains active throughout the wait standby period.
The reduction of power in the wait condition depends on how many internal clock
signals driving on-chip peripheral functions can be shut down. The CPU is always
shut down during wait. While in the wait state, the address/data bus repeatedly
runs read cycles to the address where the CCR contents were stacked. The MCU
leaves the wait state when it senses any interrupt that has not been masked.
The free-running timer system is shut down only if the I bit is set to 1 and the COP
system is disabled by NOCOP being set to 1. Several other systems also can be
in a reduced power-consumption state depending on the state of
software-controlled configuration control bits. Power consumption by the
analog-to-digital (A/D) converter is not affected significantly by the wait condition.
However, the A/D converter current can be eliminated by writing the ADPU bit to 0.
The SPI system is enabled or disabled by the SPE control bit. The SCI transmitter
is enabled or disabled by the TE bit, and the SCI receiver is enabled or disabled by
the RE bit. Therefore, the power consumption in wait is dependent on the particular
application.
Executing the STOP instruction while the S bit in the CCR is equal to 0 places the
MCU in stop mode. If the S bit is not 0, the stop opcode is treated as a no-op (NOP).
Stop mode offers minimum power consumption because all clocks, including the
crystal oscillator, are stopped while in this mode. To exit stop and resume normal
processing, a logic low level must be applied to one of the external interrupts (IRQ
or XIRQ) or to the RESET pin. A pending edge-triggered IRQ can also bring the
CPU out of stop.
Because all clocks are stopped in this mode, all internal peripheral functions also
stop. The data in the internal RAM is retained as long as V
The CPU state and I/O pin levels are static and are unchanged by stop. Therefore,
when an interrupt comes to restart the system, the MCU resumes processing as if
there were no interruption. If reset is used to restart the system, a normal reset
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Resets and Interrupts
DD
power is maintained.
Low-Power Operation
Resets and Interrupts
Data Sheet
107