C8051F34D-GQ Silicon Laboratories Inc, C8051F34D-GQ Datasheet - Page 101
C8051F34D-GQ
Manufacturer Part Number
C8051F34D-GQ
Description
IC 8051 MCU 64K FLASH 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F34xr
Specifications of C8051F34D-GQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
32-LQFP
Core Processor
8051
Core Size
8-Bit
Speed
48MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.25 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Ram Size
256 KB
Interface Type
UART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F340DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F34D-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F34D-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
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11.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V
V
typically less than 0.3 ms. Figure 11.2. plots the power-on and V
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The V
power-on reset.
Software can force a power-on reset by writing ‘1’ to the PINRSF bit in register RSTSRC.
RST
. A Power-On Reset delay (T
Logic HIGH
Logic LOW
2.70
2.4
2.0
1.0
Figure 11.2. Power-On and V
RST
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
V
RST
PORDelay
Power-On
Reset
) occurs before the device is released from reset; this delay is
T
PORDelay
Rev. 1.3
DD
Monitor Reset Timing
DD
Monitor
Reset
VDD
monitor reset timing.
DD
monitor is enabled following a
VDD
t
DD
settles above
101
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