MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 936

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Development Support
Figure 23-6
23-22
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Gives an ability to control the execution of the processor and maintain control on it under all
circumstances. The development port is able to force the CPU to enter to the debug mode even
when external interrupts are disabled.
It is possible to enter debug mode immediately out of reset thus allowing debugging of a ROM-less
system.
It is possible to selectively define, using an enable register, the events that will cause the machine
to enter into the debug mode.
When in debug mode detect the reason upon which the machine entered debug mode by reading a
cause register.
Entering into the debug mode in all regular cases is restartable in the sense that it is possible to
continue to run the regular program from the location where it entered the debug mode.
When in debug mode all instructions are fetched from the development port but load/store accesses
are performed on the real system memory.
Data Register of the development port is accessed using mtspr and mfspr instructions via special
load/store cycles. (This feature together with the last one enables easy memory dump & load).
Upon entering debug mode, the processor gets into the privileged state (MSR[PR] = 0). This
allows execution of any instruction, and access to any storage location.
An OR signal of all exception cause register (ECR) bits (ECR_OR) enables the development port
to detect pending events while already in debug mode. An example is the ability of the
development port to detect a debug mode access to a non existing memory space.
illustrates the debug mode logic implemented in the CPU.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor