MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 934

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Development Support
economical interface (three pins) that allows the development system to operate in a lower frequency than
the frequency of the CPU. Note that it is also possible to debug the CPU using monitor debugger software,
for more information refer to
Section 23.5, “Software Monitor Debugger
Support.”
Debug mode is a state where the CPU fetches all instructions from the development port. In addition, when
in debug mode, data can be read from the development port and written to the development port. This
allows memory and registers to be read and modified by a development tool (emulator) connected to the
development port.
For protection purposes, two possible working modes are defined: debug mode enable and debug mode
disable. These working modes are selected only during reset. For more information refer to
Section 23.3.1.1, “Debug Mode Enable vs. Debug Mode
Disable.”
The user can work in debug mode starting from reset or the CPU can be programmed to enter debug mode
as a result of a predefined list of events. These events include all possible interrupts and exceptions in the
CPU system, including the internal breakpoints, together with two levels of development port requests
(masked and non-masked) and one peripheral breakpoint request that can be generated by any one of the
peripherals of the system (including internal and external modules). Each event can be programmed either
to be treated as a regular interrupt that causes the machine to branch to its interrupt vector, or to be treated
as a special interrupt that causes debug mode entry.
When in debug mode an rfi instruction will return the machine to its regular work mode. The debugger
tool should issue an isync instruction to the debug port prior to any other instructions when the CPU enters
debug mode after running code.
The relationship between the debug mode logic to the rest of the CPU chip is shown in
Figure
23-5.
MPC561/MPC563 Reference Manual, Rev. 1.2
23-20
Freescale Semiconductor

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