MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 896

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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CDR3 Flash (UC3F) EEPROM
CENSOR[0:1] transitions are listed as follows:
21.3.12 Background Debug Mode or Freeze Operation
While in background debug mode, the UC3F should respond normally to accesses except that LOCK is
writable. See the LOCK bit in
21-34
1. Cleared censorship to no censorship, T1
2. No censorship to information censorship, T2
3. Information censorship, no censorship or unknown to cleared censorship, T3
4. Cleared censorship to information censorship, T4
Set CENSOR[0] or CENSOR[1].
Set CENSOR[0] and CENSOR[1].
Clear CENSOR[0:1]. This is done only while the entire UC3F array is erased.
Set both CENSOR[0] and CENSOR[1].
Table
MPC561/MPC563 Reference Manual, Rev. 1.2
21-3.
Freescale Semiconductor

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