MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 882

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

CDR3 Flash (UC3F) EEPROM
During power up and power down periods, it is assumed that the reset signal is asserted to prevent
accidental program/erase disturb of the UC3F array.
21.3.2
The UC3F EEPROM control registers are accessible for read or write operation at all times while the
device is powered up and enabled except during reset.
21.3.3
The UC3F EEPROM array is available for a read operation under most conditions while the device is
powered up. Reads of the array are not allowed in the following instances:
The address of an incoming read access is compared to the address for which data is currently held in the
read page buffers. If the data corresponding to the read address is currently held in one of the two read page
buffers, the data is fetched from the appropriate read page buffer. A data fetch from a read page buffer is
an on-page read operation
in one of the read page buffers, 32 bytes of information is fetched from the UC3F array, and the addressed
data is driven onto the data bus. A data fetch from the UC3F array is an off-page read operation.
For information regarding how the two read page buffers in the UC3F EEPROM are associated to array
blocks, refer to
The UC3F module is configured as a page mode memory. The UC3F module uses an internal address
comparator to monitor incoming addresses to determine if the addressed information is stored in a read
page buffer. When the address comparator determines that the requested information is not stored in a read
page buffer, an array off-page read operation retrieves 32 bytes of data from the Flash array and transfers
the addressed data to the data bus.
In the MPC563, the UC3F module contains two 32-byte read page buffers. In the module, one buffer is
dedicated to the most recently accessed instruction fetches and the other read page buffer is dedicated to
the most recently loaded data access.
21-20
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•
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During reset—When in information or cleared censorship with ACCESS = 0
While the UC3F EEPROM is disabled—See
disabling the UC3F EEPROM
While the UC3F EEPROM is in STOP mode—See
information on STOP mode
While high voltage is applied to the array during program and erase
operation —HVS = 1 or EHV = 1 and not suspended
Register Read and Write Operation
Array Read Operation
After setting/clearing UC3FCTL[HSUS], reset, programming writes, erase
interlock write, setting EHV, clearing SES or setting/clearing SIE, the page
buffers may not contain valid information. The UC3F forces an off-page
read before an on-page read can be accomplished to ensure data coherency.
Section 21.2.2, “UC3F EEPROM Array
Section 21.3.3.1, “Array On-Page Read
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
Section 21.3.10,
Addressing.”
Section 21.3.9, “Stop
Operation.” If the data is not contained
“Disabled,” for more information on
Operation,” for more
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