MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 864

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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CDR3 Flash (UC3F) EEPROM
The UC3F EEPROM module array is divided into array blocks to allow for independent erase, address
attributes restrictions, and protection from program and erase for each array block. The size of a large array
block in the UC3F module is fixed at 64 Kbytes. The size of a subdivided large block becomes the original
large array block size minus 16 Kbytes (64 Kbytes – 16 Kbytes = 48 Kbytes). The size of the small block,
which is the remainder of the large block, is always 16 Kbytes. The total UC3F EEPROM array is
distributed into eight large blocks, two of which contain small blocks. Information is transferred to the
UC3F EEPROM by long-word (64 bits), word (32 bits), half-word (16 bits), or byte (8 bits).
To improve system performance, each array read access retrieves 32 bytes of information. These 32 bytes
may be copied into one of two read page buffers aligned to the low order addresses. The two read page
buffers are independently updated by page management logic contained in the BIU which interfaces to the
UC3F EEPROM module.
21-2
B0EPEE
VFLASH
EPEE
VDDF
VSSF
U-Bus
Figure 21-1. Block Diagram for a 512 Kbyte UC3F Module Configuration
Memory Interface (MI)
Internal
Timer
MPC561/MPC563 Reference Manual, Rev. 1.2
Program/Erase
Read Control
Program/Erase
Control
Generation
Voltage
Bus Interface Unit (BIU)
UC3F Array Core
Register
Block
Pgm Data
Block 0 (16 Kbytes + 48 Kbytes)
Block 1 (48 Kbytes + 16 Kbytes)
Block 2 (64 Kbytes)
Block 3 (64 Kbytes)
Block 4 (64 Kbytes)
Block 5 (64 Kbytes)
Block 6 (64 Kbytes)
Block 7 (64 Kbytes)
Latch
Column Decode
Data Mux
Read Page Buffer 0
Read Page Buffer 1
Freescale Semiconductor

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