MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 855

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Chapter 20
Dual-Port TPU3 RAM (DPTRAM)
The dual-port RAM (DPTRAM) module with TPU3 microcode storage support consists of a control
register block and an 8-Kbyte array of static RAM, which can be used either as a microcode storage for
TPU3 or as a general-purpose memory. The MPC561/MPC563 has one DPTRAM module. The module
serves two TPU3 modules (A and B).
The DPTRAM module acts as a common memory on the IMB3 and allows the transfer of data to the two
TPU3 modules. Therefore, the DPTRAM interface includes an IMB3 bus interface and two TPU3
interfaces. When the DPTRAM is being used in microcode mode, the array is only accessible to the TPU3
via a separate local bus, and not via the IMB3.
In the MPC561/MPC563, the DPTRAM base address register (RAMBAR) must be set to a particular value
to fit into the IMB memory map of the part. The DPTRAM RAMBAR register must be programmed to
0xFFA0.
The DPTRAM module is powered by V
RAM if standby power is supplied via the IRAMSTBY pin of the MPC561/MPC563. IRAMSTBY must
be supplied by an external source.
The DPTRAM may also be used as the microcode control store for up to two TPU3 modules when placed
in a special emulation mode. In this mode the DPTRAM array may only be accessed by either or both of
the TPU3 units simultaneously via separate emulation buses, and not via the IMB3.
The DPTRAM contains a multiple input signature calculator (MISC) in order to provide RAM data
corruption checking. The MISC reads the DPTRAM address and generates a 32-bit data-dependent
signature. This signature can then be checked by the host.
20.1
Freescale Semiconductor
Eight Kbytes of static RAM
Accessible by the CPU only if neither TPU3 is in emulation mode
Low-power stop operation
— Entered by setting the STOP bit in the DPTMCR
— Does not enter low-power state while in TPU3 emulation mode for protection
TPU3 microcode mode
Features
The RCPU cannot perform instruction fetches from any module on the
IMB3 (including the DPTRAM). Only data accesses are permitted.
MPC561/MPC563 Reference Manual, Rev. 1.2
DD
in normal operation. The entire array may be used as standby
NOTE
20-1

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