MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 845

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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19.4.5
The channel interrupt enable register (CIER) allows the CPU to enable or disable the ability of individual
TPU3 channels to request interrupt service. Setting the appropriate bit in the register enables a channel to
make an interrupt service request; clearing a bit disables the interrupt.
19.4.6
Encoded 4-bit fields within the channel function select registers specify one of 16 time functions to be
executed on the corresponding channel. Encodings for predefined functions are found in
Table
Freescale Semiconductor
SRESET
10:15
Bits
Bits
0:15
0:4
5:7
8:9
D-2.
Field CH
Addr
Channel Interrupt Enable Register (CIER)
Channel Function Select Registers (CFSRn)
MSB
CH[15:0]
15
Name
Name
0
CIRL
ILBS
CH
14
1
Reserved
Channel interrupt request level. This three-bit field specifies the interrupt request level for all
channels. This field is used in conjunction with the ILBS field to determine the request level of
TPU3 interrupts.
Interrupt level byte select. This field and the CIRL field determine the level of TPU3 interrupt
requests.
00 IRQ[0:7] selected
01 IRQ[8:15] selected
10 IRQ[16:23] selected
11 IRQ[24:31] selected
Reserved. Note that bits 10:11 represent channel interrupt base vector (CIBV) bits in some TPU3
implementations.
Channel interrupt enable/disable
0 Channel interrupts disabled
1 Channel interrupts enabled
NOTE: The MSB (bit 0) represents CH15, and the LSB (bit 15) represents CH0.
CH
13
2
Figure 19-9. CIER — Channel Interrupt Enable Register
CH
12
3
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 19-11. CIER Bit Descriptions
CH
Table 19-10. TICR Bit Description
11
4
0x30 400A (TPU_A), 0x30 440A (TPU_B)
CH
10
5
CH 9 CH 8 CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0
0000_0000_0000_0000
6
7
Description
Description
8
9
10
11
12
13
Time Processor Unit 3
Table D-1
14
LSB
15
and
19-15

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