MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 839

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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0x30 400A(TPU_A)
0x30 440A(TPU_B)
0x30 400C(TPU_A)
0x30 440C(TPU_B)
0x30 400E(TPU_A)
0x30 401A(TPU_A)
0x30 401C(TPU_A)
0x30 441C(TPU_B)
0x30 401E(TPU_A)
0x30 402A(TPU_A)
0x30 442A(TPU_B)
0x30 402C(TPU_A)
0x30 442C(TPU_B)
0x30 402E(TPU_A)
0x30 442E(TPU_B)
0x30 4008(TPU_A)
0x30 4408(TPU_B)
0x30 4010(TPU_A)
0x30 4410(TPU_B)
0x30 4012(TPU_A)
0x30 4412(TPU_B)
0x30 4014(TPU_A)
0x30 4414(TPU_B)
0x30 4016(TPU_A)
0x30 4416(TPU_B)
0x30 4018(TPU_A)
0x30 4418(TPU_B)
0x30 4020(TPU_A)
0x30 4420(TPU_B)
0x30 4022(TPU_A)
0x30 4422(TPU_B)
0x30 4024(TPU_A)
0x30 4424(TPU_B)
0x30 4026(TPU_A)
0x30 4426(TPU_B)
0x30 4028(TPU_A)
0x30 4428(TPU_B)
Address
Table 19-6. TPU3 Register Map (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
TPU3 Interrupt Configuration Register (TICR)
See
Channel Interrupt Enable Register (CIER)
See
Channel Function Selection Register 0 (CFSR0)
See
Channel Function Selection Register 1 (CFSR1)
See
Channel Function Selection Register 2 (CFSR2)
See
Channel Function Selection Register 3 (CFSR3)
See
Host Sequence Register 0 (HSQR0)
See
Host Sequence Register 1 (HSQR1)
See
Host Service Request Register 0 (HSRR0)
See
Host Service Request Register 1 (HSRR1)
See
Channel Priority Register 0 (CPR0)
See
Channel Priority Register 1 (CPR1)
See
Channel Interrupt Status Register (CISR)
See
Link Register (LR)
Service Grant Latch Register (SGLR)
Decoded Channel Number Register (DCNR)
TPU Module Configuration Register 2 (TPUMCR2)
See
TPU Module Configuration 3 (TPUMCR3)
See
Internal Scan Data Register (ISDR)
Internal Scan Control Register (ISCR)
Table 19-10
Table 19-11
Table 19-12
Table 19-12
Table 19-12
Table 19-12
Table 19-13
Table 19-13
Table 19-14
Table 19-14
Table 19-15
Table 19-15
Table 19-17
Table 19-18
Table 19-21
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Register
Time Processor Unit 3
19-9

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