MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 793

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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17.11.1 MPIOSM Features
17.11.2 MPIOSM Signal Functions
Table 17-32
or reading from the DR.
17.11.3 MPIOSM Description
17.11.3.1 MPIOSM Port Function
A MIOS14 parallel port I/O submodule can handle up to 16 input/output signals. The number of I/O
signals is determined at the time of silicon implementation.
The MPIOSM has two 16-bit registers: the data register (DR) and the data direction register (DDR). Each
signal of the MPIOSM may be programmed as an input or an output, determined by the state of the
corresponding bit in the DDR.
The data direction register can be written to or read by the processor. During the programmed output state,
a read of the data register reads the value of the output data latch and not the I/O signal. See
and
During reset, all MPIOSM signals are configured as inputs. The contents of the data register are undefined
after reset.
As a general practice, it is recommended to write a value in the data register before configuring its
corresponding I/O signal as an output.
17.11.3.2 Non-Bonded MPIOSM Pads
A non-bonded MPIOSM pad reads ‘0’ when it is configured as an input. When configured as an output, it
indicates the current state of the output data latch.
Freescale Semiconductor
Table
Performed
Operation
A submodule of the MIOS14 library
Uses two 16-bit registers in the address space
Up to 16 bidirectional parallel input/output signals
Simple DDR (data direction register) concept for signal direction selection
Write
Write
Read
Read
17-32.
shows the MPIOSM I/O signal functions according to the setting of the DDR when writing to
DDR
0
1
0
1
Table 17-32. MPIOSM I/O Signal Function
MPC561/MPC563 Reference Manual, Rev. 1.2
The I/O signal is in input mode. The state of the I/O signal is read.
The I/O signal is in input mode. Data is written into the DR.
Data is written into the DR and output to the I/O signal.
The I/O signal is in an output mode. The DR is read.
I/O Signal Function
Modular Input/Output Subsystem (MIOS14)
Figure 17-30
17-61

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