MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 777

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Freescale Semiconductor
12:15
MDASM Control Register Bits
Bits
9:10
7:8
11
6
FORCB
MODE
Name
BSL
MODE
—
—
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
Force B bit — In the OCB, OCAB and OPWM modes, the FORCB bit allows the software to force
the output flip-flop to behave as if a successful comparison had occurred on channel B (except
that the FLAG line is not activated). Writing a one to FORCB resets the output flip-flop; writing a
zero to it has no effect.
In the DIS, IPWM, IPM and IC modes, the FORCB bit is not used and writing to it has no effect.
FORCB is cleared by reset and is always read as zero.
Writing a one to both FORCA and FORCB simultaneously resets the output flip-flop.
Reserved
Bus select bits — These bits are used to select which of the six 16-bit counter buses is used by
the MDASM. Each MDASM instance has four possible counter buses that may be connected.
See
NOTE: Unconnected counter buses inputs are grounded.
Reserved
Mode select bits — The four mode select bits select the mode of operation of the MDASM. To
avoid spurious interrupts, it is recommended that MDASM interrupts are disabled before
changing the operating mode.
The mode select bits are cleared by reset.
NOTE: The reserved modes should not be set; if these modes are set, the MDASM behavior is
undefined.
Table 17-21. MDASMSCR Bit Descriptions (continued)
Table 17-23
MPC561/MPC563 Reference Manual, Rev. 1.2
Resolution
Table 17-22. MDASM Mode Selects
Bits of
for more information.
—
16
16
16
16
16
—
—
16
15
14
13
12
11
Bus Bits
Counter
Ignored
0,1
0-2
0-3
0-4
—
—
—
—
—
—
—
—
—
0
Description
DIS – Disabled
IPWM – Input pulse width measurement
IPM – Input period measurement
IC – Input capture
OCB – Output compare, flag on B compare
OCAB – Output compare, flag on A and B compare
Reserved
Reserved
OPWM – Output pulse width modulation
OPWM – Output pulse width modulation
OPWM – Output pulse width modulation
OPWM – Output pulse width modulation
OPWM – Output pulse width modulation
OPWM – Output pulse width modulation
MDASM Mode of Operation
Modular Input/Output Subsystem (MIOS14)
17-45