MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 765

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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17.9.3.5
Output compare mode (either OCA or OCB) is selected by setting MODE[0:3] to 0b010x. The MODE0
controls the activation criteria for the FLAG line, (i.e., when a compare occurs only on channel B or when
a compare occurs on either channel).
This mode allows the MDASM to perform four different output functions:
In this mode the leading and trailing edges of variable width output pulses are generated by calculated
output compare events occurring on channels A and B, respectively. OC mode may also be used to perform
a single output compare function, or may be used as an output port bit.
In this mode, channel B is accessed via register B2. A write to register B2 writes the same value to register
B1 even though the contents of B1 are not used in this mode. Both channels work together to generate one
‘single shot’ output pulse signal. Channel A defines the leading edge of the output pulse, while channel B
defines the trailing edge of the pulse. FLAG line activation can be done when a match occurs on channel
B only or when a compare occurs on either channel (as defined by the MODE0 in the MDASMSCR
register).
When this mode is first selected, (i.e., coming from disable mode, both comparators are disabled). Each
comparator is enabled by writing to its data register; it remains enabled until the next successful
comparison is made on that channel, whereupon it is disabled. The values stored in registers A and B are
compared with the count value on the selected 16-bit counter bus when their corresponding comparators
are enabled.
Freescale Semiconductor
Counter Bus
Mode selection; EDPOL = 0 (Channel A capture on rising edge)
Input signal
Internal Register, not accessible to software
Register B1
16-bit
Register B2
Register A
FLAG bit
(Ignored)
Single-shot output pulse (two edges), with FLAG line activated on the second edge
Single-shot output pulse (two edges), with FLAG line activated on both edges
Single-shot output transition (one edge)
Output port signal, with output compare function disabled
Output Compare (OCB and OCAB) Modes
0x0500
0xxxxx
0xxxxx
0xxxxx
Edge Trigger
Figure 17-18. MDASM Input Capture Example
Flag set
Rising
0x1000
MPC561/MPC563 Reference Manual, Rev. 1.2
0x1000
0x1000
0xxxxx
FLAG reset
by software
0x1000
0x1100
0x1000
0xxxxx
Edge Trigger
0x1400
0x1400
0x1000
Flag set
0x1400
Rising
FLAG reset
by software
Modular Input/Output Subsystem (MIOS14)
0x1400
0x1400
0x1000
0x1525
Flag set
Edge Trigger
0x16A0
0x16A0
0x1400
FLAG reset
by software
Rising
0x16A0
17-33

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