MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 722

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

CAN 2.0B Controller Module
16.7.5
16-28
SRESET
CNRX0
Signal
Bits
8:15
2:3
4:5
6:7
0
1
Field
Addr
Control Register 1 (CANCTRL1)
1
2
CANCTRL1
MSB
BOFFMSK
TXMODE[1:0]
RXMODE
ERRMSK
TXMODE
Full CMOS drive indicates that both dominant and recessive levels are driven by the chip.
Open drain drive indicates that only a dominant level is driven by the chip. During a recessive
level, the CNTX0 signal is disabled (three stated), and the electrical level is achieved by external
pull-up/pull-down devices. The assertion of both Tx mode bits causes the polarity inversion to be
cancelled (open drain mode forces the polarity to be positive).
0
RX1
Name
X
X
—
1X
00
01
1
0x30 7086 (CANCTRL1_A); 0x30 7486 (CANCTRL1_B); 0x30 7886 (CANCTRL1_C)
RX0
0
1
2
Bus off interrupt mask. The BOFF MASK bit provides a mask for the bus off interrupt.
0 Bus off interrupt disabled
1 Bus off interrupt enabled
Error interrupt mask. The ERRMSK bit provides a mask for the error interrupt.
0 Error interrupt disabled
1 Error interrupt enabled
Reserved
Receive signal configuration control. These bits control the configuration of the CNRX0
signals. Refer to
Transmit signal configuration control. This bit field controls the configuration of the CNTX0
signals. Refer to
See
CANCTRL0
Full CMOS
Full CMOS
Open drain
3
0 CNRX0 signal is interpreted as a dominant bit
1 CNRX0 signal is interpreted as a recessive bit
0 CNRX0 signal is interpreted as a recessive bit
1 CNRX0 signal is interpreted as a dominant bit
Table 16-16
Figure 16-12. Control Register 1 (CANCTRL1)
Table 16-15. Transmit Signal Configuration
Table 16-14. Rx MODE[1:0] Configuration
Table 16-13. CANCTRL0 Bit Descriptions
MPC561/MPC563 Reference Manual, Rev. 1.2
4
1
1
2
5
; positive polarity (CNTX0 = 0 is a dominant level)
; negative polarity (CNTX0 = 1 is a dominant level)
; positive polarity
Table
Table
and
6
Section 16.7.5, “Control Register 1
16-14.
16-15.
0000_0000_0000_0000
TransmitSignal Configuration
7
SAMP
Receive Signal Configuration
8
Description
—
9
TSYNC LBUF
10
(CANCTRL1).”
11
—
12
Freescale Semiconductor
13
PROPSEG
14
LSB
15