MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 656

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Queued Serial Multi-Channel Module
15.6.5.8
Wraparound mode is enabled by setting the WREN bit in SPCR2. The queue can wrap to pointer address
0x0 or to the address pointed to by NEWQP, depending on the state of the WRTO bit in SPCR2.
In wraparound mode, the QSPI cycles through the queue continuously, even while the QSPI is requesting
interrupt service. SPE is not cleared when the last command in the queue is executed. New receive data
overwrites previously received data in receive RAM. Each time the end of the queue is reached, the SPIF
flag is set. SPIF is not automatically reset. If interrupt-driven QSPI service is used, the service routine must
clear the SPIF bit to end the current interrupt request. Additional interrupt requests during servicing can
be prevented by clearing SPIFIE, but SPIFIE is buffered. Clearing it does not end the current request.
Wraparound mode is exited by clearing the WREN bit or by setting the HALT bit in SPCR3. Exiting
wraparound mode by clearing SPE is not recommended, as clearing SPE may abort a serial transfer in
progress. The QSPI sets SPIF, clears SPE, and stops the first time it reaches the end of the queue after
WREN is cleared. After HALT is set, the QSPI finishes the current transfer, then stops executing
commands. After the QSPI stops, SPE can be cleared.
15-38
Master Wraparound Mode
PCS_IN[3:0]
PCS_IN[3:0] is driven from QSMCM module. PCS_OUT[7:0] will be
driven from the pads to the pins. If the bits PCS4EN, PCS5EN, PCS6EN,
PCS7EN are negated (logic 0), PCS_OUT[3:0] will be the same as
PCS_IN[3:0]. The design assumes that if one of these enable bits is set, PCS
function is selected in QSMCM module.
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 15-22. PCS Enhanced Functionality (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
PCS_OUT[7:0] IF PCSV = 0
RESERVED
00001000
00010000
00100000
01000000
10000000
00000000
NOTE
PCS_OUT[7:0] IF PCSV = 1
RESERVED
11110111
11101111
11011111
10111111
01111111
11111111
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