MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 638

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Queued Serial Multi-Channel Module
15.6.1.3
SPCR2 contains QSPI queue pointers, wraparound mode control bits, and an interrupt enable bit. The CPU
has read/write access to SPCR2, but the QSPI has read access only. Writes to this register are buffered.
New SPCR2 values become effective only after completion of the current serial transfer. Rewriting
NEWQP in SPCR2 causes execution to restart at the designated location. Reads of SPCR2 return the
current value of the register, not the buffer.
15.6.1.4
SPCR3 contains the loop mode enable bit, halt and mode fault interrupt enable, and the halt control bit.
The CPU has read/write access to SPCR3, but the QSPI has read access only. SPCR3 must be initialized
before QSPI operation begins. Writing a new value to SPCR3 while the QSPI is enabled disrupts operation.
15-20
SRESET
11:15
Bits
8:10
3:7
Field SPIFIE WREN WRTO
Addr
0
1
2
NEWQP
MSB
ENDQP
QSPI Control Register 2 (SPCR2)
QSPI Control Register 3 (SPCR3)
SPIFIE
WREN
WRTO
Name
0
—
1
SPI finished interrupt enable. Refer to
0 QSPI interrupts disabled
1 QSPI interrupts enabled
Wrap enable. Refer to
0 Wraparound mode disabled.
1 Wraparound mode enabled.
Wrap to. When wraparound mode is enabled and after the end of queue has been reached,
WRTO determines which address the QSPI executes next. The end of queue is determined by
an address match with ENDQP.
0 Wrap to pointer address 0x0
1 Wrap to address in NEWQP
Ending queue pointer. This field determines the last absolute address in the queue to be
completed by the QSPI. After completing each command, the QSPI compares the queue pointer
value of the just-completed command with the value of ENDQP. If the two values match, the QSPI
sets SPIF to indicate it has reached the end of the programmed queue. Refer to
“QSPI
Reserved
New queue pointer value. This field contains the first QSPI queue address. Refer to
Section 15.6.4, “QSPI
Operation” for more information.
2
Figure 15-13. SPCR2 — QSPI Control Register 2
MPC561/MPC563 Reference Manual, Rev. 1.2
3
Table 15-16. SPCR2 Bit Descriptions
4
Section 15.6.5.8, “Master Wraparound
Operation” for more information.
ENDQP
5
0000_0000_0000_0000
6
0x30 501C
Section 15.6.4.2, “QSPI
7
Description
8
—
9
10
Mode.”
Interrupts.”
11
12
Freescale Semiconductor
NEWQP
Section 15.6.4,
13
14
LSB
15