MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 635

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

To ensure proper operation, set the QSPI enable bit (SPE) in SPCR1 only after initializing the other control
registers. Setting this bit starts the QSPI.
Rewriting the same value to a control register does not affect QSPI operation with the exception of writing
NEWQP in SPCR2. Rewriting the same value to these bits causes the RAM queue pointer to restart
execution at the designated location.
Before changing control bits, the QSPI should be halted. Writing a different value into a control register
other than SPCR2 while the QSPI is enabled may disrupt operation. SPCR2 is buffered, preventing any
disruption of the current serial transfer. After the current serial transfer is completed, the new SPCR2 value
becomes effective.
15.6.1.1
SPCR0 contains parameters for configuring the QSPI before it is enabled. The CPU has read/write access
to SPCR0, but the QSPI has read access only. SPCR0 must be initialized before QSPI operation begins.
Writing a new value to SPCR0 while the QSPI is enableddisrupts operation.
Freescale Semiconductor
1
2
SRESET
Access
S = Supervisor access only
S/U = Supervisor access only or unrestricted user access (assignable data space).
Eight-bit registers, such as SPCR3 and SPSR, are on 8-bit boundaries. 16-bit registers such as SPCR0 are on 16-bit
boundaries.
S/U
S/U
Field MSTR WOMQ
Addr
1
QSPI Control Register 0 (SPCR0)
MSB
0x30 51C0 –
0x30 5180 –
0
0
0x30 51BF
0x30 51DF
Address
0
1
MSB
0
2
Figure 15-11. QSPI Control Register 0 (SPCR0)
Table 15-12. QSPI Register Map (continued)
2
MPC561/MPC563 Reference Manual, Rev. 1.2
3
BITS
0000
4
5
CPOL CPHA
0
6
Transmit Data RAM (32 half-words)
0x30 5018
Command RAM (32 bytes)
1
7
8
9
10
Queued Serial Multi-Channel Module
0000_0100
11
SPBR
12
13
14
LSB
LSB
15
15
15-17