MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 560

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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QADC64E Enhanced Mode Operation
14.3.7
Control register 2 is the mode control register for the operation of queue 2. Software specifies the queue
operating mode of queue 2, and may enable a completion and/or a pause interrupt. All control register
fields are read/write data, except the SSE2 bit, which is readable only when the test mode is enabled. Most
of the bits are typically written once when the software initializes the QADC64E, and not changed
afterwards.
14-18
SRESET
Field CIE2
Addr
Control Register 2
MSB
0
0
MQ1[3:7]
PIE2 SSE2
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
0
1
0
2
Table 14-12. Queue 1 Operating Modes (continued)
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
External gated single-scan mode (started with SSE1)
Reserved mode
Software triggered continuous-scan mode
External trigger rising edge continuous-scan mode
External trigger falling edge continuous-scan mode
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
External gated continuous-scan mode
Figure 14-11. Control Register 2 (QACR2)
3
MPC561/MPC563 Reference Manual, Rev. 1.2
0x30 480E (QACR2_A), 0x30 4C0E (QACR2_B)
4
0_0000
MQ2
5
6
Operating Modes
7
RESUME
0
8
9
10
16
17
11
111_1111
BQ2
7
8
10
11
12
1
14
15
16
17
12
Freescale Semiconductor
9
13
14
LSB
15

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