MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 559

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Freescale Semiconductor
8:15
Bits
3:7
0
1
2
Name
SSE1
CIE1
PIE1
MQ1
MQ1[3:7]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
Queue 1 Completion Interrupt Enable. CIE1 enables an interrupt upon completion of
queue 1. The interrupt request is initiated when the conversion is complete for the CCW in
queue 1.
0 Disable the queue completion interrupt associated with queue 1
1 Enable an interrupt after the conversion of the sample requested by the last CCW in
Queue 1 Pause Interrupt Enable. PIE1 enables an interrupt when queue 1 enters the
pause state. The interrupt request is initiated when conversion is complete for a CCW that
has the pause bit set.
0 Disable the pause interrupt associated with queue 1
1 Enable an interrupt after the conversion of the sample requested by a CCW in queue 1
Queue 1 Single-Scan Enable Bit. SSE1 enables a single-scan of queue 1 to start after a
trigger event occurs. The SSE1 bit may be set to a one during the same write cycle when
the MQ1 bits are set for one of the single-scan queue operating modes. The single-scan
enable bit can be written as a one or a zero, but is always read as a zero. The SSE1 bit
enables a trigger event to initiate queue execution for any single-scan operation on queue
1. The QADC64E clears the SSE1 bit when the single-scan is complete. Refer to
Table 14-12
0 Trigger events are not accepted for single-scan modes
1 Accept a trigger event to start queue 1 in a single-scan mode
Queue 1 Operating Mode. The MQ1 field selects the queue operating mode for queue 1.
Table 14-12
Reserved
queue 1
which has the pause bit set
Disabled mode, conversions do not occur
Software triggered single-scan mode (started with SSE1)
External trigger rising edge single-scan mode
External trigger falling edge single-scan mode
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 14-12. Queue 1 Operating Modes
Table 14-11. QACR1 Bit Descriptions
shows the bits in the MQ1 field which enable different queue 1 operating mode
for more information.
Operating Modes
Description
QADC64E Enhanced Mode Operation
7
8
9
10
11
12
13
14
15
14-17

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