MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 548

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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QADC64E Enhanced Mode Operation
channel field of the conversion command word (CCW) table. External Multiplex mode is software
selectable, by setting the EMUX bit of control register 0 (QACR0).
Figure 14-3
The QADC provides three multiplexer address signals – MA0, MA1, MA2 – to select one of the
multiplexer chips. These outputs are the multiplexer control lines and they are connected to all external
multiplexer chips.
The analog output of each of the four multiplexer chips is connected to four separate QADC inputs – ANw,
ANx, ANy, ANz. These signals are the first four signals of port B and each one can represent eight analog
input channels. The QADC converts the proper input channel (ANw, ANx, ANy, ANz) by interpreting the
channel number in the CCW. Refer to
14-6
I
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
AN8
AN9
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN0
shows the maximum configuration of four external multiplexer chips connected to the QADC.
MUX
MUX
MUX
MUX
Multiplexed Analog Input
External Triggers:
ETRIG1
ETRIG2
ANw (AN44)
ANx (AN45)
ANy (AN46)
ANz (AN47)
AN44/ANw/PQB0
AN52/MA0/PQA0
AN53/MA1/PQA1
AN54/MA2/PQA2
Table 14-3. Multiplexed Analog Input Channels
AN46/ANy/PQB2
AN47/ANz/PQB3
AN45/ANx/PQB1
Figure 14-3. Example of External Multiplexing
MPC561/MPC563 Reference Manual, Rev. 1.2
AN48/PQB4
AN49/PQB5
AN50/PQB6
AN51/PQB7
AN55/PQA3
AN56/PQA4
AN57/PQA5
AN58/PQA6
AN59/PQA7
V SSA
V DDA
AltRef
Table
V
V RL
RH
14-3.
ANALOG REFERENCES
ANALOG POWER
16 through 23
24 through 31
8 through 15
0 through 7
MULTIPLEXER
Channels
PORT LOGIC
ANALOG
AND
CONVERTER
ANALOG
QADC
Freescale Semiconductor
DIGITAL
CONTROL

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