MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 536

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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QADC64E Legacy Mode Operation
Series resistance can be used with the capacitor on an input signal to implement a simple RC filter. The
maximum level of filtering at the input signals is application dependent and is based on the bandpass
characteristics required to accurately track the dynamic characteristics of an input. Simple RC filtering at
the signal may be limited by the source impedance of the transducer or circuit supplying the analog signal
to be measured. Refer to
cases, the size of the capacitor at the signal may be very small.
Figure 13-52
the interaction between the external circuitry and the circuitry inside the QADC64E.
In
C
to provide charge to C
The following paragraphs provide a simplified description of the interaction between the QADC64E and
the external circuitry. This circuitry is assumed to be a simple RC low-pass filter passing a signal from a
source to the QADC64E input signal. The following simplifying assumptions are made:
13-72
SAMP
Figure
is the capacitor array used to sample and hold the input voltage. V
It sources charge during the sample period when the analog signal source is a high-impedance
source.
The external capacitor is perfect (no leakage, no significant dielectric absorption characteristics,
etc.)
All parasitic capacitance associated with the input signal is included in the value of the external
capacitor
Inductance is ignored
V
R
C
C
R
C
V
13-52, R
F
F
P
SRC
SRC
I
SAMP
Source
= Filter Impedance
= Filter Capacitor
= Internal Voltage Source during Sample and Hold
= Internal Parasitic Capacitance
V
is a simplified model of an input channel. Refer to this model in the following discussion of
SRC
= Source Impedance
R
= Source Voltage
SRC
= Sample Capacitor
F
, R
SRC
SAMP
External Filter
Section 13.7.5.3, “Error Resulting from
and C
R F
Figure 13-52. Electrical Model of an A/D Input Signal
during sample phase.
C F
F
MPC561/MPC563 Reference Manual, Rev. 1.2
comprise the external filter circuit. C
Internal Circuit Model
S1
C P
AMP
Leakage,” for more information. In some
S2
QADC64E Sample AMP Model
P
I
is the internal parasitic capacitor.
is an internal voltage source used
C
SAMP
S3
Freescale Semiconductor
VI

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