MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 529

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Example 3 below shows the timing for conversions in gated continuous-scan mode with the same
assumptions in the amended definition for the PF bit in this mode to reflect the condition that a gate closing
occurred before the queue completed is a proposal under consideration at this time as example 2.
Freescale Semiconductor
Trig1
(gate)
EOC
QS
Q1 RES
SSE
CF1
PF1
CWP
CWPQ1
At the end of Q1,the completion flag CF1 sets and the queue restarts. Also,
note that if the queue starts a second time and completes, the trigger overrun
flag TOR1 sets.
LAST
0
LAST
Software must set SSE
LAST
Software must clear PF1
CCW0
Figure 13-47. Gated Mode, Single-Scan Timing
8
MPC561/MPC563 Reference Manual, Rev. 1.2
CCW0
R0
CCW1
0
CCW1
R1
NOTE
CCW0
CCW0
CCW1
R0
8
CCW2
CCW1
R1
QADC64E Legacy Mode Operation
CCW3
CCW2
R2
CCW3
R3
0
13-65

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