MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 52

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

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18-27
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Figure
Number
Short Channels Register (SHORT_CH_REG) ..................................................................... 18-23
Scale Transmit Clock Register (SCALE_TCLK_REG)....................................................... 18-24
TPU3 Block Diagram ............................................................................................................. 19-1
TPU3 Interrupt Levels ............................................................................................................ 19-5
TCR1 Prescaler Control.......................................................................................................... 19-7
TCR2 Prescaler Control.......................................................................................................... 19-8
TPUMCR — TPU Module Configuration Register ............................................................. 19-11
DSCR — Development Support Control Register ............................................................... 19-12
DSSR — Development Support Status Register .................................................................. 19-14
TICR — TPU3 Interrupt Configuration Register ................................................................. 19-14
CIER — Channel Interrupt Enable Register......................................................................... 19-15
CFSR0 — Channel Function Select Register 0 .................................................................... 19-16
CFSR1 — Channel Function Select Register 1 .................................................................... 19-16
CFSR2 — Channel Function Select Register 2 .................................................................... 19-16
CFSR3 — Channel Function Select Register 3 .................................................................... 19-16
HSQR0 — Host Sequence Register 0................................................................................... 19-17
HSQR1 — Host Sequence Register 1................................................................................... 19-17
HSRR0 — Host Service Request Register 0 ........................................................................ 19-17
HSRR1 — Host Service Request Register 1 ........................................................................ 19-17
CPR0 — Channel Priority Register 0 ................................................................................... 19-18
CPR1 — Channel Priority Register 1 ................................................................................... 19-18
CISR — Channel Interrupt Status Register .......................................................................... 19-19
TPUMCR2 — TPU Module Configuration Register 2 ........................................................ 19-19
TPUMCR3 — TPU Module Configuration Register 3 ........................................................ 19-21
SIUTST — SIU Test Register .............................................................................................. 19-22
DPTRAM Configuration ........................................................................................................ 20-2
DPTRAM Memory Map......................................................................................................... 20-3
DPT Module Configuration Register (DPTMCR).................................................................. 20-3
RAM Array Base Address Register (RAMBAR)................................................................... 20-5
Multiple Input Signature Register High (MISRH) ................................................................. 20-5
Multiple Input Signature Register Low (MISRL) .................................................................. 20-6
MISC Counter (MISCNT) ...................................................................................................... 20-6
Block Diagram for a 512 Kbyte UC3F Module Configuration .............................................. 21-2
UC3F EEPROM Configuration Register (UC3FMCR) ......................................................... 21-5
UC3FMCRE— UC3F EEPROM Extended Configuration Register ..................................... 21-9
UC3F EEPROM High Voltage Control Register (UC3FCTL) ............................................ 21-11
PEGOOD Valid Time ........................................................................................................... 21-14
Shadow Information ............................................................................................................. 21-16
Hard Reset Configuration Word (UC3FCFIG) .................................................................... 21-16
512-Kbyte Array Configuration............................................................................................ 21-19
MPC561/MPC563 Reference Manual, Rev. 1.2
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